Logo
ScienceStack
Table of Contents
Fetching ...
Sign In

HPQEA: A Scalable and High-Performance Quantum Emulator with High-Bandwidth Memory for Diverse Algorithms Support

Tran Van Duy, Tuan Hai Vu, Vu Trung Duong Le, Hoai Luan Pham, Yasuhiko Nakashima

TL;DR

HPQEA introduces a scalable quantum emulator based on state-vector simulation that combines a high-performance computing core, an optimized CX swap strategy, and high-bandwidth memory to support diverse algorithms up to 30 qubits. Implemented on an AMD Alveo U280 FPGA, it leverages dual processing element arrays, a specialized CX swapper, and HBM-based bulk data transfer to achieve high fidelity and low memory overhead. Extensive benchmarking against CPUs, GPUs, and FPGA-based emulators shows competitive performance, with significant speedups for small-to-moderate qubit counts and improved algorithm diversity, though HBM overhead limits scalability beyond ~20 qubits. The work demonstrates a practical, efficient platform for emulating quantum algorithms and guides future improvements in memory usage and resource optimization for larger-scale quantum simulations.

Abstract

In recent years, there has been a growing interest in the development of quantum emulation. However, existing studies often struggle to achieve broad applicability, high performance, and efficient resource and memory utilization. To address these challenges, we provide HPQEA, a quantum emulator based on the state-vector emulation approach. HPQEA includes three main features: a high-performance computing core, an optimized controlled-NOT gate computation strategy, and effective utilization of high-bandwidth memory. Verification and evaluation on the Alveo U280 board show that HPQEA can emulate quantum circuits with up to 30 qubits while maintaining high fidelity and low mean square error. It outperforms comparable FPGA-based systems by producing faster execution, supporting a wider range of algorithms, and requiring low hardware resources. Furthermore, it exceeds the Nvidia A100 in normalized gate speed for systems with up to 20 qubits. These results demonstrate the scalability and efficiency of HPQEA as a platform for emulating quantum algorithms.

HPQEA: A Scalable and High-Performance Quantum Emulator with High-Bandwidth Memory for Diverse Algorithms Support

TL;DR

HPQEA introduces a scalable quantum emulator based on state-vector simulation that combines a high-performance computing core, an optimized CX swap strategy, and high-bandwidth memory to support diverse algorithms up to 30 qubits. Implemented on an AMD Alveo U280 FPGA, it leverages dual processing element arrays, a specialized CX swapper, and HBM-based bulk data transfer to achieve high fidelity and low memory overhead. Extensive benchmarking against CPUs, GPUs, and FPGA-based emulators shows competitive performance, with significant speedups for small-to-moderate qubit counts and improved algorithm diversity, though HBM overhead limits scalability beyond ~20 qubits. The work demonstrates a practical, efficient platform for emulating quantum algorithms and guides future improvements in memory usage and resource optimization for larger-scale quantum simulations.

Abstract

In recent years, there has been a growing interest in the development of quantum emulation. However, existing studies often struggle to achieve broad applicability, high performance, and efficient resource and memory utilization. To address these challenges, we provide HPQEA, a quantum emulator based on the state-vector emulation approach. HPQEA includes three main features: a high-performance computing core, an optimized controlled-NOT gate computation strategy, and effective utilization of high-bandwidth memory. Verification and evaluation on the Alveo U280 board show that HPQEA can emulate quantum circuits with up to 30 qubits while maintaining high fidelity and low mean square error. It outperforms comparable FPGA-based systems by producing faster execution, supporting a wider range of algorithms, and requiring low hardware resources. Furthermore, it exceeds the Nvidia A100 in normalized gate speed for systems with up to 20 qubits. These results demonstrate the scalability and efficiency of HPQEA as a platform for emulating quantum algorithms.

Paper Structure

This paper contains 15 sections, 1 equation, 8 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Background knowledge
  3. Quantum computing
  4. Quantum simulation algorithm
  5. Proposed Hardware Architecture
  6. Overview
  7. High-Performance Dual PEAs
  8. Optimized CX Swapper
  9. Optimized HBM-Based Bulk Data Transfer
  10. Verification and Evaluation
  11. Implementation and Verification
  12. Benchmarking Methods
  13. Comparison with CPUs and GPUs
  14. Comparison with FPGA-based works
  15. Conclusion

Figures (8)

  • Figure 1: The details of the HPQEA: (a) The overview of the HPQEA system, (b) (Insect) Processing Element, (c) (Insect) Arithmetic Logic Unit, and (d) (Insect) Special Unit.
  • Figure 2: CX working flow: (a) Old version, (b) New version
  • Figure 3: High Bandwidth Memory of the Alveo U280 FPGA board.
  • Figure 4: Example of 4-qubit topologies (a-d) and (e) Decomposing of $CP(\theta)$ as a combination of $CX$ and $R_z$ gates tran2025qeaacceleratorquantumcircuit.
  • Figure 5: Comparison in execution time between HPQEA and a variety of random quantum circuits indexed from #1 to #19
  • ...and 3 more figures