Physics-Informed Optimisation of Conveyor Mode Spin Qubit Transport

TL;DR

This work tackles the challenge of scalable, high-fidelity shuttling of spin-qubits across extended silicon devices by introducing a physics-informed optimization framework that couples self-consistent Poisson–Schrödinger simulations with DC flat-band searches and AC moving-well bias design. The method ensures a constant ground-state energy $E_0$ and near-constant transport velocity $v_x$ during conveyor-mode transport, enabling propulsion of quantum states with reduced decoherence. Applied to FD-SOI, SiMOS, and SiGe platforms, the approach reveals strong dependence of shuttle fidelity on gate geometry, dielectric interfaces, and quantum-dot size, with $E_1 - E_0$ staying above about $0.5\,\mathrm{meV}$ in favorable cases and tunneling occurring when geometry or biases are unfavorable. Overall, the framework provides a scalable pathway toward coherent interconnects in large-scale silicon quantum processors, with potential extensions to include decoherence effects and real-time adaptive control for dynamic environments.

Abstract

Scalable quantum information processing in spin-based architectures necessitates the a bility to reliably shuttle quantum states across extended device regions with minimal decoherence. In this work, we present a physics-informed algorithm for optimizing electrostatic bias equences that enable conveyor-mode electron transport in silicon-based quantum dot devices. Our approach combines self-consistent Poisson and Schrodinger solvers to maintain a constant ground state energy and enable near-constant velocity shuttling, with potential applicability to both single-electron and hole transport. We validate the algorithm across three representative technologies: Fully-Depleted Silicon on Insulator (FD-SOI), Silicon Metal-Oxide-Seminconductor (SiMOS) and Silicon-Germanium Heterostracture (Si/SiGe), highlighting key limitations and material-specific effects that influence transport fidelity. Our findings underscore the impact of gate geometry, dielectric interfaces, and quantum dot size on the stability of shuttling operations, and offer pathways toward improving coherence preservation in large-scale quantum systems.

Figures (6)

• Figure 1: The symbolic workflow of the used framework.
• Figure 2: AC and DC voltages applied to the shuttling gates. (a) A DC voltage that provides a flat conduction band. (b) Net AC and DC voltages that create a conveyor mode shuttling. (c) An AC voltage is applied to the gates.
• Figure 3: An example that shows how different stages of the algorithm works. (a) The cartoon layout of the test structure. R0 and R1 represent the reservoirs; A0 and A1 are the accumulation gates; T0 and T1 are the tunnelling gates; J0, J1, J2, J3 and J4 are the J-gates. (b) Different stages of the DC bias definition algorithm. Different colours represent different iterations of the algorithm from 0 to 4. The thick black line shows the result. Black circles on the graph represent the points selected for the optimisation. (c) The quantum dot formed under the J1 gate (the wavefunction is normalised to be visible). (d) The quantum dot formed under the T0 gate (the wavefunction is normalised to be visible). (e) The quantum dot formed under the J2 gate (the wavefunction is normalised to be visible). (f) The time-evolution of both conduction band edge --- the contour plot, and the probability density function --- the colour mesh.
• Figure 4: An example of the intermediate step of the AC-voltage definition algorithm. (a) Voltages applied to different gates. (b) Coordinate $X(t)$ of the quantum dot --- solid blue line. If the quantum dot were to move with a constant speed, the coordinate would change as shown by the green dash-dot line. The solid red line with circles represents the speed of the quantum dot. The constant speed is the orange dashed line.
• Figure 5: Summary of the FD-SOI simulations. (a) 3D image of the quantum device: buried oxide --- yellow; raised source and drain that are doped --- deep blue; undoped silicon channel --- light blue; gate oxide --- green; polysilicon gate --- red; tungsten J-gates --- olive; metal contacts --- orange; spacer --- transparent gray. (b) Optimal AC voltages are applied for the different gates for the conveyor mode shuttling. (c) Ground-state energy --- blue dashed line; The first excited state energy --- orange dashed line. Energy difference --- green filling. (d) The coordinate $X$ over time --- blue line, with the constant speed coordinate over time --- red dashed line. The size of the quantum dot $\Delta X$ ---orange dashed line. (e) The version of the same device without J-gates. Here is the same colour legend as in Figure \ref{['fig:example_fdsoi']} a. (f) Optimised gate voltages applied to the device without J-gates. (g) The ground state energy and the first excited state energy evolution with time. (h) The coordinate and the size of the quantum dot evolution.