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Breaking the Treewidth Barrier in Quantum Circuit Simulation with Decision Diagrams

Bin Cheng, Ziyuan Wang, Ruixuan Deng, Jianxin Chen, Zhengfeng Ji

TL;DR

The paper challenges the treewidth barrier in classical quantum circuit simulation by introducing a FeynmanDD-based analysis whose complexity scales as $2^{O(lrw(G_C))}$, where $lrw$ is the linear rank-width of the circuit's variable graph. It shows that for circuit families with small $lrw$, FeynmanDD can outperform tensor-network methods, and, via Solovay-Kitaev gate expansion, extends applicability to arbitrary gate sets. The authors provide rigorous bounds linking DD size to $lrw$ and show that compiling continuous gates increases $lrw$ only by at most 2, preserving the overall exponential-in-$lrw$ behavior. Numerical experiments corroborate the theoretical advantages on lrw-bounded circuits and reveal practical trade-offs for real-world circuits like Google's supremacy benchmarks, suggesting avenues for further optimization and integration with existing tensor-network approaches.

Abstract

Classical simulation of quantum circuits is a critical tool for validating quantum hardware and probing the boundary between classical and quantum computational power. Existing state-of-the-art methods, notably tensor network approaches, have computational costs governed by the treewidth of the underlying circuit graph, making circuits with large treewidth intractable. This work rigorously analyzes FeynmanDD, a decision diagram-based simulation method proposed in CAV 2025 by a subset of the authors, and shows that the size of the multi-terminal decision diagram used in FeynmanDD is exponential in the linear rank-width of the circuit graph. As linear rank-width can be substantially smaller than treewidth and is at most larger than the treewidth by a logarithmic factor, our analysis demonstrates that FeynmanDD outperforms all tensor network-based methods for certain circuit families. We also show that the method remains efficient if we use the Solovay-Kitaev algorithm to expand arbitrary single-qubit gates to sequences of Hadamard and T gates, essentially removing the gate-set restriction posed by the method.

Breaking the Treewidth Barrier in Quantum Circuit Simulation with Decision Diagrams

TL;DR

The paper challenges the treewidth barrier in classical quantum circuit simulation by introducing a FeynmanDD-based analysis whose complexity scales as , where is the linear rank-width of the circuit's variable graph. It shows that for circuit families with small , FeynmanDD can outperform tensor-network methods, and, via Solovay-Kitaev gate expansion, extends applicability to arbitrary gate sets. The authors provide rigorous bounds linking DD size to and show that compiling continuous gates increases only by at most 2, preserving the overall exponential-in- behavior. Numerical experiments corroborate the theoretical advantages on lrw-bounded circuits and reveal practical trade-offs for real-world circuits like Google's supremacy benchmarks, suggesting avenues for further optimization and integration with existing tensor-network approaches.

Abstract

Classical simulation of quantum circuits is a critical tool for validating quantum hardware and probing the boundary between classical and quantum computational power. Existing state-of-the-art methods, notably tensor network approaches, have computational costs governed by the treewidth of the underlying circuit graph, making circuits with large treewidth intractable. This work rigorously analyzes FeynmanDD, a decision diagram-based simulation method proposed in CAV 2025 by a subset of the authors, and shows that the size of the multi-terminal decision diagram used in FeynmanDD is exponential in the linear rank-width of the circuit graph. As linear rank-width can be substantially smaller than treewidth and is at most larger than the treewidth by a logarithmic factor, our analysis demonstrates that FeynmanDD outperforms all tensor network-based methods for certain circuit families. We also show that the method remains efficient if we use the Solovay-Kitaev algorithm to expand arbitrary single-qubit gates to sequences of Hadamard and T gates, essentially removing the gate-set restriction posed by the method.

Paper Structure

This paper contains 15 sections, 9 theorems, 28 equations, 4 figures, 5 tables, 1 algorithm.

Table of Contents

  1. Introduction
  2. Preliminaries
  3. Sum-of-powers representation
  4. Decision diagrams and Feynman decision diagrams
  5. Rank-width and linear rank-width
  6. Time complexity of FeynmanDD
  7. Gate set $\mathcal{T}$ and $\mathcal{G}$
  8. Gate set $\mathcal{R}$
  9. Factor graph, tensor network and variable graph
  10. Compiling continuous gates into discrete gates
  11. Time complexity of building decision diagrams
  12. Provable advantage over tensor networks
  13. Linear-network circuits
  14. Linear rank-width construction
  15. Numerical experiments

Key Result

Proposition 2.1

Let $k$ be a positive parameter. Given an $n$-vertex graph $G$, we can output a linear ordering of $G$ of width at most $k$ or confirm that the linear rank-width of $G$ is larger than $k$ in time $\order{f(k) \cdot n^3}$, where $f$ is a computable function.

Figures (4)

  • Figure 1: Quantum circuits and graphs. (a) A quantum circuit $C'$ constructed from the gate set $\mathcal{T}$. (b) A quantum circuit $C$ constructed from the gate set $\mathcal{R}$, which has the same unitary as the circuit $C'$. Here, we let $R_1 = \mathrm{H} \mathrm{T} \mathrm{H}$, $R_2 = \mathrm{T} \mathrm{H}$, $R_3 = \mathrm{H}$, and $R_4 = \mathrm{H} \mathrm{T}$. (c) The tensor network of the circuit $C$. (d) The variable graph (and the factor graph) of the circuit $C'$. (e) The factor graph of the circuit $C$. (f) The line graph of the tensor network in (c).
  • Figure 2: Let $C$ be a quantum circuit constructed from gate set $\mathcal{R}$, with variable graph $G_C$ (left panel). Let $C'$ be a quantum circuit compiled from $C$ using the Solovay-Kitaev algorithm, with variable graph $G_{C'}$ (right panel).
  • Figure 3: A linear network for computing Boolean functions. Figure adapted from Knu09.
  • Figure 4: Left: A subcircuit of circuit specified by \ref{['eq:small_bdd_f']} with $\vb*{\alpha} = (0, 1, 0, 1, 1)$. Right: The corresponding subgraph forming a lattice.

Theorems & Definitions (17)

  • Proposition 2.1
  • Theorem 3.1
  • proof
  • Theorem 3.2
  • proof
  • Theorem 3.3
  • proof
  • Theorem 3.4
  • proof
  • Theorem 4.1: Theorem M of Knu09
  • ...and 7 more