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Batched high-rate logical operations for quantum LDPC codes

Qian Xu, Hengyun Zhou, Dolev Bluvstein, Madelyn Cain, Marcin Kalinowski, John Preskill, Mikhail D. Lukin, Nishad Maskara

TL;DR

A near-term implementation using new self-dual Bivariate-Bicycle codes with high encoding rates, transversal Clifford gates, and global $T$ gates via parallel magic state cultivation is proposed, enabling Hamiltonian simulations with a lower space-time cost than analogous surface-code protocols and low-rate qLDPC protocols.

Abstract

High-rate quantum LDPC (qLDPC) codes reduce memory overhead by densely packing many logical qubits into a single block of physical qubits. Here we extend this concept to high-rate computation by constructing \emph{batched} fault-tolerant operations that apply the same logical gate across many code blocks in parallel. By leveraging shared physical resources to execute many logical operations in parallel, these operations realize high rates in space-time and significantly reduce computational costs. For \emph{arbitrary} CSS qLDPC codes, we build batched gadgets with \emph{constant space-time overhead} (assuming fast classical computation) for (i) single-shot error correction, state preparation, and code surgeries (ii) code switching, and (iii) addressable Clifford gates. Using these batched gadgets we also construct parallel non-Clifford gates with low space-time cost. We outline principles for designing parallel quantum algorithms optimized for a batched architecture, and show in particular how lattice Hamiltonian dynamical simulations can be compiled efficiently. We also propose a near-term implementation using new self-dual Bivariate-Bicycle codes with high encoding rates ($\sim 1/10$), transversal Clifford gates, and global $T$ gates via parallel magic state cultivation, enabling Hamiltonian simulations with a lower space-time cost than analogous surface-code protocols and low-rate qLDPC protocols. These results open new paths toward scalable quantum computation via co-design of parallel quantum algorithms and high-rate fault-tolerant protocols.

Batched high-rate logical operations for quantum LDPC codes

TL;DR

A near-term implementation using new self-dual Bivariate-Bicycle codes with high encoding rates, transversal Clifford gates, and global gates via parallel magic state cultivation is proposed, enabling Hamiltonian simulations with a lower space-time cost than analogous surface-code protocols and low-rate qLDPC protocols.

Abstract

High-rate quantum LDPC (qLDPC) codes reduce memory overhead by densely packing many logical qubits into a single block of physical qubits. Here we extend this concept to high-rate computation by constructing \emph{batched} fault-tolerant operations that apply the same logical gate across many code blocks in parallel. By leveraging shared physical resources to execute many logical operations in parallel, these operations realize high rates in space-time and significantly reduce computational costs. For \emph{arbitrary} CSS qLDPC codes, we build batched gadgets with \emph{constant space-time overhead} (assuming fast classical computation) for (i) single-shot error correction, state preparation, and code surgeries (ii) code switching, and (iii) addressable Clifford gates. Using these batched gadgets we also construct parallel non-Clifford gates with low space-time cost. We outline principles for designing parallel quantum algorithms optimized for a batched architecture, and show in particular how lattice Hamiltonian dynamical simulations can be compiled efficiently. We also propose a near-term implementation using new self-dual Bivariate-Bicycle codes with high encoding rates (), transversal Clifford gates, and global gates via parallel magic state cultivation, enabling Hamiltonian simulations with a lower space-time cost than analogous surface-code protocols and low-rate qLDPC protocols. These results open new paths toward scalable quantum computation via co-design of parallel quantum algorithms and high-rate fault-tolerant protocols.

Paper Structure

This paper contains 45 sections, 21 theorems, 92 equations, 22 figures, 4 tables, 1 algorithm.

Key Result

Theorem 1

Given a $[n_C, k_C, d_C]$ classical LDPC code with sufficient expansion and $k_C$ blocks of any $[[n, k, d]]$ qLDPC CSS code $\mathcal{Q}$ with $d_C \geq d$, we can perform a round of stabilizer measurement for $Q^{\otimes k_C}$ fault-tolerantly using $2(n_C-k_C)$ ancillary $\mathcal{Q}$ blocks and

Figures (22)

  • Figure 1: Overview of new high-rate logical operations and efficiently implementable parallel quantum algorithms. High-rate qLDPC codes (b) save space costs over low-rate codes (a) by sharing physical qubits within a code block among the many encoded logical qubits. Analogously, high-rate logical operations (d) save space-time costs over low-rate operations (c) by sharing physical gates among the many encoded logical operations. In this work, we introduce new classes of high-rate logical operations by operating on multiple high-rate qLDPC blocks in batches. These batched operations support space-time-efficient implementations of quantum algorithms with a parallel structure. For instance, a brickwork circuit (f) can be implemented using batched logical gates that involve mostly high-rate transversal gates on batched high-rate qLDPC blocks. This also enables simulating quantum dynamics of lattice Hamiltonians (g) using algorithms that involve brickwork circuits, e.g. the HHKL algorithm haah2021quantum.
  • Figure 2: Batched syndrome extraction. Compared to the standard protocol (a), where each quantum code’s syndromes are protected by disjoint, low-rate repetition codes along the time direction---requiring $\mathcal{O}(d_C)$ code cycles---the BSE gadget (b) protects syndromes with a joint, high-rate $[n_C, k_C, d_C]$ classical code spanning multiple quantum codes in the spatial direction, reducing the time cost to a constant depth. (c) We illustrate a concrete implementation of BSE with the $[7,4,3]$ Hamming code $\mathcal{C}$, whose Tanner graph is shown in (b). By applying transversal CNOTs, information about syndrome errors are transferred to each orange ancilla code block, based on the structure of $\mathcal{C}$. The circuit detectors are obtained by comparing the transversal $X$ measurements with the round of noisy $X$ syndromes, and effectively form metachecks that ensure no low-weight syndrome error goes undetected. (d) Numerical simulations of BSE are performed using a distance-$d$ toric code $T_d$ for the qLDPC code, and either a $[7,4,3]$ Hamming code hamming1950error or a $[12,3,6]$ quasi-cyclic code xu2024fast for the classical BSE code. We simulate the circuit in (c) for preparing a batch of logical $\ket{0}$ states in single shot under standard circuit-level depolarizing noise, excluding idling errors. Note, the logical error rate includes so-called "time-like logical errors", which are sensitive to syndrome errors. The results are compared against standard syndrome extraction repeated $d$ times (dashed lines), and shows that BSE achieves similar performance with only $O(1)$ spacetime overhead.
  • Figure 3: Batched code switching and addressable Clifford gates. (a): A batched code-switching (BCS) gadget that converts between $k_2$ blocks of a $[[n_1, k_1, d_1]]$ CSS qLDPC code $\mathcal{Q}_1$ (a column colored in gray) and $k_1$ blocks of another $[[n_2, k_2, d_2]]$ CSS qLDPC code $\mathcal{Q}_2$ (a row colored in blue), during which the $i$-th logical qubit of the $j$-th $\mathcal{Q}_1$ block, $\mathcal{Q}_1^{(j)}$, is routed to the $j$-th logical qubit of the $i$-th $\mathcal{Q}_2$ block, $\mathcal{Q}_2^{(i)}$ (see the first and third logical operators colored in pink and green, respectively, of $\mathcal{Q}_1^{(1)}$). The physical implementation can be visualized on a 2D grid: $k_2$ columns of $\mathcal{Q}_1$, along with $n_2 - k_2$ ancilla $\mathcal{Q}_1$ initialized in logical $\ket{0}$ or $\ket{+}$, are first entangled into a joint $n_1 n_2$-qubit intermediate code via measuring the $\mathcal{Q}_2$ checks, where the logical operators are delocalized across the grid, and then disentangled into $k_1$ rows of $\mathcal{Q}_2$ via transversal measurements on the complementary rows. (b) A batched addressable Clifford (BAC) gadget that implements an in-block addressable Clifford gate $C$ on a batch of $k_2$$\mathcal{Q}_1$ blocks by BCS to $k_1$ blocks of $\mathcal{Q}_2$ and implementing $C$ transversally.
  • Figure 4: Parallel non-Clifford gates. (a) Batched code switching enables parallel non-Clifford gates in a $[[n_1, k_1, d_1]]$ CSS qLDPC code $\mathcal{Q}_1$ by switching to/from $k_1$ copies of a $[[n_3,1,d_3=\mathcal{O}(\log n_1)]]$ code $\mathcal{Q}_3$ with transversal $T$ gates (e.g., 3D color codes). Global logical $T$ gates on a target $\mathcal{Q}_1$ block can be implemented via either $T$ measurements (left) or $|T\rangle$-state injection (right) on an ancillary $\mathcal{Q}_1$ block using the BCS gadget. The $T$ measurement scheme requires only Pauli feedforward on the target code, as opposed to local Clifford gates with higher compilation cost. (b) Parallel magic state cultivation for a $[[n_b,k_b,d_b]]$ BB code $\mathcal{Q}_{\mathrm{BB}}$ with disjoint logical operators $\{\bar{X}_i\}_{i \in [k_b]}$. The protocol transfers $k_b$ high-fidelity $\ket{T}$ states cultivated in small 2D color codes gidney2024magic into $\mathcal{Q}_{\mathrm{BB}}$ in parallel, each via an interface of a thin surface code and modified adapter systems swaroop2024universal. The final $\ket{T}^{k_b}$ states are stored in the merged $[[n>n_b,k=k_b,d\sim d_b]]$ color-surface-BB code $\mathcal{Q}_{\mathrm{CSBB}}$ shown in (b). (c) Logical error rates (per logical qubit) of cultivated $\ket{T}^{\otimes 6}$ states stored in $[[216,6,5]]$ (green star) and $[[324,6,7]]$ (pink diamond) $\mathcal{Q}_{\mathrm{CSBB}}$, starting from $[[42,6,6]]$ and $[[66,6,8]]$$\mathcal{Q}_{\mathrm{BB}}$, compared to $\mathcal{Q}_{\mathrm{BB}}$ memory logical error rates (per logical qubit, per code cycle) (dashed).
  • Figure 5: Fault-tolerant compilation with batched logical gates. Structured circuits (a) with parallel gates can be compiled more efficiently than unstructured circuits (b) using batched gadgets. We illustrate fault-tolerant implementations of a structured (a) and an unstructured (b) logical CNOT circuit with the BAC gadgets (Theorem \ref{['theorem:batched_Cliffords']}) on a batch of qLDPC-encoded sectors (gray blocks). In (a), the circuit decomposes into two layers of parallel gates with identical distributions across $\mathcal{Q}_1$ blocks, requiring only two BAC gadgets. In contrast, (b) lacks parallel structure, forcing serial execution with the number of BAC gadgets scaling with the logical block size of the qLDPC code.
  • ...and 17 more figures

Theorems & Definitions (41)

  • Theorem 1: Batched syndrome extraction
  • Theorem 2: Batched code switching
  • Theorem 3: Batched addressable Cliffords
  • Theorem 4: Parallel non-Clifford gates
  • Corollary 5: Batched state preparation
  • proof
  • Definition 6: Canonical basis of CSS codes gottesman1997stabilizer
  • Definition 7: Measurement-based encoding/decoding protocol for any CSS code
  • Lemma 8: Size of the batched gadgets $\mathbf{B}_L$
  • proof
  • ...and 31 more