Fault-tolerant interfaces for modular quantum computing on diverse qubit platforms

TL;DR

The work tackles fault-tolerant interconnects for modular quantum computing, assessing how to efficiently wire together QPUs with surface-code protection. It introduces grow-and-distil, a strategy that interleaves code growth with distillation to cut qubit overhead while delivering high-rate logical Bell pairs, and compares it against lattice surgery and transversal gates across diverse hardware. Through analytical bounds and cross-platform simulations, it identifies operational regimes where each method is optimal, showing that grow-and-distil can dramatically reduce resource needs (thousands of networking qubits) and that efficient interconnects depend strongly on Bell-pair quality, entangling rates, and memory budgets. The results offer concrete guidance for experimental platforms (neutral atoms, SiV defects, superconducting qubits) and motivate exploration of higher-encoding-rate codes (e.g., $q$LDPC) to further alleviate networking demands while maintaining fault tolerance.

Abstract

Modular architectures offer a scalable path toward fault-tolerant quantum computing by interconnecting smaller quantum processing units (QPUs) provided that high-rate, fault-tolerant interfaces can be realized across modules. We present a comprehensive analysis and comparison of known and new methods for establishing such interfaces, including lattice surgery, transversal gates, and novel grow-and-distil protocols based on code growing and logical distillation. Using the surface code, we identify optimal interface strategies across a wide range of hardware parameters, such as gate fidelities, entangling rates, and memory resources, and estimate the requirements to achieve logical error rates of $10^{-6}$ and $10^{-12}$. Our results establish when the interface become a bottleneck in the computation and provide guidance for experimental implementations with superconducting, atomic, and solid-state hardware.

Figures (8)

• Figure 1: (a) Distributed algorithm between two nodes, requiring local logical gates (black) as well as distributed logical gates (orange), both with high fidelity. (b) Physical implementation of two nodes, each with a computation zone and a network zone, with physical Bell pairs distributed between both nodes. We are assuming there is a direct quantum connection between qubits in network and computation zones. Three main approaches for fault-tolerant distributed QC are presented in (c-d). (c) Injection and logical distillation interleaved with growing (grow-and-distil). (d) Lattice surgery (e) Transversal gate.
• Figure 2: Rate of distributed logical Bell pairs $r_\mathrm{distributed}$ as a function of local memory dedicated to distillation. The two $x$-axes represent the amount of allocated space for distillation in terms of physical qubits (upper) and logical qubits (lower) respectively. Includes rates from both distillation with code growing and distillation without code growing (NG) with a target Bell pair error rate of $10^{-12}$. The figure is made assuming physical Bell pairs are produced at a rate equal to the time of local physical gates. Other parameters are initial physical Bell pair error rate of 1%, physical gate error rate of 0.1%, and idling errors per physical gate of $10^{-6}$.
• Figure 3: Rate of distributed logical Bell pairs $r_\mathrm{distributed}$ as a function of physical Bell pair rate $r_\mathrm{bell}$. These are given in units of local logical gate rates and physical gate rates respectively. Rates from each of the three methods: Distillation, logical CNOT by lattice surgery, and transversal logical CNOT are included. The figure is for initial physical Bell pair error rate of 1%, a target Bell pair error rate $10^{-12}$, with allocated memory of 10 000 physical qubits, physical gate error rate of 0.1%, and idling errors per physical gate of $10^{-6}$.
• Figure 4: Logical Bell pair distribution rate $r_{\mathrm{distributed}}$ as a function of networking memory and physical Bell pair rate $r_{\mathrm{bell}}$. The two plots correspond to (top) $p_{\mathrm{bell}} = 1\%$, $p_{\mathrm{target}} = 10^{-12}$ and (bottom) $p_{\mathrm{bell}} = 5\%$, $p_{\mathrm{target}} = 10^{-6}$. Rates are expressed in units of the local physical gate rate $r_{\mathrm{physical}}$ and local syndrome extraction rate $r_{\mathrm{logical}}$. The $y$-axes show both physical (right) and logical (left) qubit counts. Each point reflects the highest rate achievable among the three methods: distillation, lattice surgery, and transversal gates. Black contour lines divide regions with different optimal methods. The full-white regions extending from the bottom left represent parameter regimes where no method achieves the target error rate. Discrete jumps are due to the discrete nature of surface code sizes and distillation protocols, and are not artifacts of resolution. Expected operational regions for neutral atoms, SiV, and superconducting qubits are outlined, each extending left and downward from the indicated boundaries.
• Figure 5: (Left) The two solid lines illustrate the rates produced by the optimal sequences in the limit of low $S'$ and high Bell pair rate $S"$. Together, they provide the maximal distillation rate for most cases. Only for input rates between $C_{S'}$ and $C_{S"}$ can sequences exist that further improve on these rates. Furthermore, the optimum is known to be restricted to within the gray shaded area. (Right) The distillation rate for allocated space of 13565 physical qubits and target error $p_{target}=10^{-12}$. The solid line is the bound given by the reduced search. The dashed line is the enhanced bound induced by solutions for space <13565, and the dotted line is the true maximum rate.