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CMOS 2.0 -- Redefining the Future of Scaling

Moritz Brunion, Navaneeth Kunhi Purayil, Francesco Dell'Atti, Sebastian Lam, Refik Bilgic, Mehdi Tahoori, Luca Benini, Julien Ryckaert

TL;DR

The paper argues that deterministic geometric scaling of CMOS is reaching fundamental limits and DTCO-driven methods alone cannot sustain progress. It proposes CMOS 2.0, a heterogeneous 3D stacking platform enabled by fine-pitch hybrid bonding and backside processing, paired with a functionality-driven partitioning framework and architecture- and EDA-aware design flows. It outlines three architectural thrusts—3D enhancements, micro-architectural innovations, and novel paradigms—along with reliability and Silicon Lifecycle Management to address scaling challenges. By enabling dense, heterogeneous, vertically integrated compute and memory, CMOS 2.0 aims to continue performance and energy improvements while leveraging the existing CMOS ecosystem, albeit with new toolchains and design methodologies.

Abstract

We propose to revisit the functional scaling paradigm by capitalizing on two recent developments in advanced chip manufacturing, namely 3D wafer bonding and backside processing. This approach leads to the proposal of the CMOS 2.0 platform. The main idea is to shift the CMOS roadmap from geometric scaling to fine-grain heterogeneous 3D stacking of specialized active device layers to achieve the ultimate Power-Performance-Area and Cost gains expected from future technology generations. However, the efficient utilization of such a platform requires devising architectures that can optimally map onto this technology, as well as the EDA infrastructure that supports it. We also discuss reliability concerns and eventual mitigation approaches. This paper provides pointers into the major disruptions we expect in the design of systems in CMOS 2.0 moving forward.

CMOS 2.0 -- Redefining the Future of Scaling

TL;DR

The paper argues that deterministic geometric scaling of CMOS is reaching fundamental limits and DTCO-driven methods alone cannot sustain progress. It proposes CMOS 2.0, a heterogeneous 3D stacking platform enabled by fine-pitch hybrid bonding and backside processing, paired with a functionality-driven partitioning framework and architecture- and EDA-aware design flows. It outlines three architectural thrusts—3D enhancements, micro-architectural innovations, and novel paradigms—along with reliability and Silicon Lifecycle Management to address scaling challenges. By enabling dense, heterogeneous, vertically integrated compute and memory, CMOS 2.0 aims to continue performance and energy improvements while leveraging the existing CMOS ecosystem, albeit with new toolchains and design methodologies.

Abstract

We propose to revisit the functional scaling paradigm by capitalizing on two recent developments in advanced chip manufacturing, namely 3D wafer bonding and backside processing. This approach leads to the proposal of the CMOS 2.0 platform. The main idea is to shift the CMOS roadmap from geometric scaling to fine-grain heterogeneous 3D stacking of specialized active device layers to achieve the ultimate Power-Performance-Area and Cost gains expected from future technology generations. However, the efficient utilization of such a platform requires devising architectures that can optimally map onto this technology, as well as the EDA infrastructure that supports it. We also discuss reliability concerns and eventual mitigation approaches. This paper provides pointers into the major disruptions we expect in the design of systems in CMOS 2.0 moving forward.

Paper Structure

This paper contains 17 sections, 5 figures.

Table of Contents

  1. Introduction
  2. Towards CMOS 2.0
  3. The CMOS scaling challenge
  4. The premise of CMOS 2.0
  5. A functionality-driven CMOS 2.0 technology stack
  6. Architecture
  7. 3D enhancements to existing architectures
  8. Micro-architectural innovations for 3D
  9. Novel architectural paradigms
  10. Electronic Design Automation
  11. Towards EDA for very fine pitch 3D stacks
  12. Towards EDA for highly heterogeneous very fine pitch 3D stacks
  13. Reliability
  14. Reliability Wall in Advanced Technology Nodes
  15. Breaking Through the Reliability Wall with CMOS 2.0
  16. ...and 2 more sections

Figures (5)

  • Figure 1: CMOS 2.0 versus 3D-IC
  • Figure 2: CMOS 2.0 emerging from hybrid bonding and double-sided processing
  • Figure 3: Four potential fine-grain partitioning in digital systems
  • Figure 4: Block diagram of a typical parallel system depicting various functional elements blocks at the chiplet, cluster, and the level.
  • Figure 5: High-level examples of conceptual CMOS 2.0 stacks. Each rectangle represents a - pair and is labeled with its optimization target. Further, each rectangle is annotated with a function through the function-color map introduced in Fig. \ref{['fig:arch_template']}.