A Dense and Efficient Instruction Set Architecture Encoding
Emad Jacob Maroun
TL;DR
The paper proposes Scry, a novel ISA designed to maximize encoding density and efficiency by abandoning register-based data flow in favor of forward-temporal referencing and internal tagging of operand types. Forward-temporal referencing specifies when outputs are consumed, reducing false dependencies and enabling operand-count polymorphism, while internal tagging allows a single encoding to support multiple data types and semantics. The combination yields 16-bit instructions with substantially higher encoding efficiency than traditional ISAs such as RV64IMC, and a flexible ALU encoding scheme that supports multiple output patterns without bloating the encoding space. Initial evaluation via hand-written assemblies shows that small Scry functions have density comparable to RV64IMC, while larger functions become denser due to reduced need for register spilling and prologue/epilogue overhead, highlighting significant potential for dense, extensible code. The work lays a foundation for a compiler and processor to realize these benefits in practice, with substantial implications for performance, power, and area in modern processors.
Abstract
Instruction density and encoding efficiency are some of the few things directly affected by an instruction set architecture's design. In contrast, a processor's implementation often significantly influences performance, power efficiency, and area usage. Therefore, a major goal of instruction set design should be maximizing instruction density and encoding efficiency. This paper introduces the design elements of the Scry instruction set architecture that most significantly affect instruction density and encoding efficiency. Scry is a novel and experimental instruction set that revisits first principles to design an instruction set fit for modern processor implementations. Scry uses forward-temporal referencing as a means of data flow, where instructions refer to which future instructions consume their outputs. It also uses internal tagging, where the processors track data types internally, to reduce the number of instructions needed and increase flexibility. Combining these two methods, Scry achieves instruction-feature parity with RISC-V's RV64IMC using only 2-byte instructions compared to RISC-V's 4 bytes. Scry's instructions occupy only 28% of the 2-byte encoding space, where RV64IMC instructions occupy 68% of the 4-byte encoding space. We show that hand-compiled Scry's static instruction density is comparable to RV64IMC for small functions and improves as functions grow in size.