Optimizing Phase-Scheduling with Throughput Trade-offs in AQFP Digital Circuits

TL;DR

AQFP scalability is hampered by path-balancing buffers required for clock-phase alignment. This work proposes a unified ILP that jointly optimizes clock phase assignment and buffer insertion by combining phase-skipping and phase-alignment, using an alpha/beta decomposition of buffering costs. The minimum-area solution achieves on average $25\%$ area reduction over phase-skipping and $11\%$ over phase-alignment, and a throughput-aware extension yields $2.62\times$ higher throughput with $6.8\%$ area savings relative to the state-of-the-art phase-aligned method. These results demonstrate meaningful area and performance gains and provide a principled framework for future AQFP design flows, including non-row-based placements and scalable heuristics for large circuits.

Abstract

Adiabatic Quantum-Flux-Parametron (AQFP) logic is a promising emerging superconducting technology for ultra-low power digital circuits, offering orders of magnitude lower power consumption than CMOS. However, AQFP scalability is challenged by excessive buffer overhead due to path balancing technology constraints. Addressing this, recent AQFP works have proposed design solutions to reduce path balancing overhead using phase-skipping and phase-alignment. Phase-skipping is a circuit-level technique that allows data transfer between AQFP gates clocked with non-consecutive clock phases. In contrast, phase-alignment is an architectural approach involving repeating input patterns to allow data transfer between AQFP gates across multiples of full clock cycles. While both techniques individually mitigate the area overhead of path-balancing, they have not yet been jointly explored. In this work, we present the first clock phase scheduling algorithm that combines phase-skipping and phase-alignment. We first present a minimum area method that on average, achieves a 25% area reduction compared to phase-skipping alone and a 11% reduction compared to phase-alignment. We then extend the method to enforce a target throughput, enabling efficient area-performance trade-offs. With our throughput constrained optimization, we achieve on average 6.8% area savings with a 2.62x increased throughput compared to the state-of-the-art phase-aligned method.

Figures (6)

• Figure 1: Circuit Construction of AQFP Buffer. Current directions shown for when flux is in the left loop, corresponding to a logical "1".
• Figure 2: Buffer insertion along highly imbalanced paths for various clocking schemes (off path fan-ins/fanouts omitted for clarity). Imbalances in logical gates are often magnified by the insertion of clocked splitters to achieve fanout.
• Figure 3: When c6288 is mapped to AQFP technology with balanced splitter trees inserted, over 50% of logic gates have an imbalance in inputs exceeding 9 levels. The average imbalance is 32.6 levels.
• Figure 4: Buffer insertion costs for each clocking scheme based on level imbalances. (Phase alignment is shown with 8-phases highlight features in comparison to 8-phase phase-skipping circuits)
• Figure 5: Buffer insertion costs become aperiodic when cycle-skipping constraints are enforced. When $S_{max} = 1$, buffers must be inserted to limit each connection to span only 1 cycle.