3D Electronic-Photonic Heterogenous Interconnect Platforms Enabling Energy-Efficient Scalable Architectures For Future HPC Systems

TL;DR

This work targets the energy and bandwidth bottlenecks of next-generation HPC interconnects by introducing a 3D-Chiplet stacked electronic-photonic interconnect platform (3D-EPIC) that carries high-speed data in the optical domain using TSOVs, while maintaining TSVs for power delivery and short-reach electrical links. A formal FoM is defined to compare interconnects across bandwidth density, energy efficiency, and latency, and the analysis suggests optical interconnects can surpass copper for longer in-package links, especially when WDM is leveraged. The authors present progress on TSOV fabrication, 3D EIC-PIC integration with Direct Bond Interconnect (DBI) bonding, and a coherent transceiver architecture that achieves substantial reductions in parasitics and energy per bit, outlining a clear path toward ≤100 fJ/bit. The platform promises scalable, energy-efficient HPC interconnects capable of >10 TB/s/mm^2 bandwidth density, enabling true disaggregation and global optical connectivity for future AI workloads.

Abstract

3D interconnects have emerged as a solution to address the scaling issues of interconnect bandwidth and the memory wall problem in high-performance computing (HPC), such as High-Bandwidth Memory (HBM). However, the copper-based electrical interconnect retains fundamental limitations. Dense I/O for high-speed signals lead to degraded signal quality for end-to-end links, necessitating additional circuits to mitigate signal impairments and resulting in poor energy efficiency. We propose a 3D chiplet stacking electronic-photonic interconnect (EPIC) platform, which offers a solution by moving the high-speed data communication interface to the optical domain across the 3D stack by using Through Silicon Optical Vias (TSOV), while retaining the functionality of electrical TSVs and 2.5D interconnects for power delivery and short-reach low-latency communications. We then benchmark the proposed model against state-of-the-art 3D electrical interconnects to demonstrate our 3D EPIC platform beating the 3D electrical interconnects to $>$10 TB/s/$mm^2$ bandwidth density. We present a pathway to extend our demonstrated, industry-ready design to achieving $\leq$100 fJ/bit high-speed communication.

Figures (15)

• Figure 1: Comparison of interconnect technologies performance Figure of Merit (FoM) (Gbps/mm)/(pJ/bit)*(mm/ns) for the link length or reach of a typical implementation.
• Figure 2: Proposed 3DChiplet-to-3DChiplet Electronic-Photonic Interconnect (3D-EPIC) platform. Scalable, energy-efficient, with massively parallel bandwidth throughput capabilities, with in-package optical interconnect and seamless optical connectivity to off-package optical interconnect.
• Figure 3: Comparing energy efficiencies for a copper interconnect and an optical interconnect at 8 Gbps datarate.
• Figure 4: The total bandwidth density of a theoratical 3D optical interconnect vs the projected UCIe-3D standard. The optical interconnect here assumes a fixed channel datarate, and WDM channel count per TSOV.
• Figure 5: Total achievable bandwidth of a theoratical 3D optical interconnect compared against the projected UCIe-3D standard plotted vs the die size set by the die edge length. The optical interconnect here assumes a fixed number of 32 channels at 32 Gbps datarate per channel, and the electrical bump pitch is fixed to 55$\mu$m.