Advancing Plasmonic Computing with Single-Beam Logic Primitives

TL;DR

This work tackles the scalability barrier in plasmonic logic posed by interferometric designs and auxiliary control signals. It introduces a single-beam, single-global-threshold (SGT) mechanism implemented on a plasmonic two-wire transmission line (TWTL) that leverages polarization-selective modes and geometry-driven phase control to realize deterministic logic without external inputs. The authors demonstrate a suite of circuit primitives—2-bit comparator, parity checkers, and encoder/decoder—by coherently combining branch signals at a single output with a global threshold, achieving up to a 67% footprint reduction and ~50% power saving compared to cascaded approaches, while maintaining speed and stability. This source-free, polarization-controlled framework advances plasmonic nanocircuitry toward scalable, energy-efficient optical processors that can be integrated with silicon photonics for wafer-scale architectures.

Abstract

Plasmonic logic circuits combine ultrafast operation with nanoscale integration, making them a strong candidate for next-generation optical computing. Realizing this potential, however, requires overcoming practical challenges such as bulky interferometric designs and reliance on secondary control signals. This work advances plasmonic logic by introducing a single-global threshold mechanism in plasmonic two-wire transmission lines, empowered with polarization modal selectivity and geometric tuning to enable versatile circuit functionality. The scheme embeds the control signal with a single laser beam, supporting six deterministic polarization states and eliminating the need for auxiliary inputs. With this framework, we experimentally demonstrate advanced logic operations, including a 2-bit comparator, parity checkers, and encoder/decoder circuits. The approach reduces circuit footprint by 67% and power consumption by 50% relative to state-of-the-art systems, while maintaining low latency and high stability. By unifying thresholding, polarization, and geometry into a compact, source-free scheme, this work pushes plasmonic nanocircuitry from device-level novelty toward scalable, energy-efficient architectures for next-generation optical processors.

Figures (5)

• Figure 1: Single-beam TWTL primitive and comparator establishing the single-global threshold (SGT) criterion. (a) Working principle illustrated with simulated intensity maps. A dimer input routes polarization-programmed SPPs into branches $A$ and $B$. The single-stub mode detector is read only at the outer scatter (Out). Numbers indicate normalized intensities at the branch termini and at Out (dashed circle). Equal, sub-threshold inputs ($A\!=\!B$) add constructively at the outer port to realize $(0,0)\!\rightarrow\!1$; asymmetric routing (linear $\pm45^{\circ}$) yields an imbalanced pair with a weak superposition at the outer port $(1,0)/(0,1)\!\rightarrow\!0$; circular polarization produces the largest branch-contrast and a strong constructive sum, giving Out $=1$. Inset shows dimer antenna parameters $(w,a,b)$ used in the simulations. (b) SEM image of the gold half-circuit comparator (two open branches, no mode detector). (c) Experimental validation of input classification with corresponding polarization labels and the same normalized threshold ($I_{\mathrm{th}}=0.7$). The four panels show $A\!=\!B$ (0$^{\circ}$, both sub-threshold), $A\!>\!B$ (RHCP), $A\!<\!B$ (LHCP), and $A\!=\!B$ (90$^{\circ}$, both above threshold). The terminal-intensity ratios reproduce the intended input states and anchor the SGT used for all subsequent circuits.
• Figure 2: Parity checkers. (a) SEM image of the dimer-based even-parity device. (b) Output maps with $I_{\mathrm{th}}=0.75$. The top panel shows experiment and the bottom panel shows numerical results. LHCP and RHCP route SPPs into a single branch which yields $(0,1\!\to\!1)$ and $(1,0\!\to\!1)$ at the readout, the $90^{\circ}$ state equalizes branch amplitudes and projects anti-symmetrically to give $(1,1\!\to\!0)$. (c) SEM image of the link-based odd-parity device. (d) Output maps with $I_{\mathrm{th}}=0.755$. The top panel shows experiment and the bottom panel shows numerical simulations. The $0^{\circ}$ state keeps both termini low yet phase aligned so the outer port adds to $(0,0\!\to\!1)$, LHCP or RHCP brighten both branches in phase to give $(1,1\!\to\!1)$, linear $\pm45^{\circ}$ bias one branch and weaken the projected field to give $(1,0\!\to\!0)$ and $(0,1\!\to\!0)$.
• Figure 3: Encoder. (a) SEM image of the 4–to-2 encoder built from two three-branch units. Path-length offsets impose $\Delta\phi(Y_{0},Y_{3})\approx\pi$ and set the companion branch of $Y_{3}$ in phase at the readout to program addition or cancellation. (b) Output maps with $I_{\mathrm{th}}=0.55$. The top panel shows experiment and the bottom panel shows numerical results. Columns from left to right use input polarizations $-45^{\circ}$, $90^{\circ}$, $0^{\circ}$, and $+45^{\circ}$. For $-45^{\circ}$ the routing selects $Y_{0}$ and both ports are arranged anti-phase so $(0,0,0,1)\!\rightarrow\!(0,0)$. For $90^{\circ}$ the fields add at $A_{0}$ and oppose at $A_{1}$ so $(0,0,1,0)\!\rightarrow\!(0,1)$. For $0^{\circ}$ the relative phase is flipped so $(0,1,0,0)\!\rightarrow\!(1,0)$. For $+45^{\circ}$ the routing favors $Y_{3}$ with an in-phase companion so both ports add and $(1,0,0,0)\!\rightarrow\!(1,1)$. Coherent superposition at each port follows the phase-engineered paths and yields the desired input-output combinations.
• Figure 4: Decoder. (a) SEM image of the 2-to–4 decoder that maps inputs $(A_{1},A_{0})$ to one-hot outputs $(Y_{3},Y_{2},Y_{1},Y_{0})$ by path-engineered phase and modal projection at each readout. (b) Output maps with $I_{\mathrm{th}}=0.6$. The top panel shows experiment and the bottom panel shows numerical results. Columns use input polarizations $0^{\circ}$, $-45^{\circ}$, $+45^{\circ}$, and $90^{\circ}$. For $0^{\circ}$ constructive interference is designed only at $Y_{0}$ so $(0,0)\!\rightarrow\!(0,0,0,1)$. For $-45^{\circ}$ the routing and phase set addition at $Y_{1}$ so $(0,1)\!\rightarrow\!(0,0,1,0)$. For $+45^{\circ}$ constructive interference occurs at $Y_{2}$ so $(1,0)\!\rightarrow\!(0,1,0,0)$. For $90^{\circ}$ the antisymmetric mode brightens $Y_{3}$ so $(1,1)\!\rightarrow\!(1,0,0,0)$. The same threshold is applied at all ports and the observed intensities match the designed superposition.
• Figure : Advancing Plasmonic Computing with Single-Beam Logic Primitives