Algorithmic Tradeoff Exploration for Component Placement and Wire Routing in Nanomodular Electronics
Peidi Song, Alexandros Daglis, Michael Filler, Ahmed Saeed
TL;DR
The paper tackles per-circuit design automation in nanomodular electronics, where imprecise component deposition makes placement and routing a critical, non-amortized task. It adapts classical design automation steps—partitioning, floorplanning, placement, and routing—to NE constraints, employing simulated annealing for placement and BFS/weighted A* routing to balance time-to-solution against total wire length $\Psi$. Key findings show that end-to-end manufacturing time $Et$ can be accelerated by up to $108\times$ with only a modest $21\%$ increase in $\Psi$, and that semantic-aware partitioning plus inter-block routing can yield substantial reductions in both runtime and wiring needs. The results underscore NE’s potential for rapid prototyping and on-demand manufacturing, enabling high-flexibility electronics with manageable tradeoffs between circuit quality and manufacturing speed.
Abstract
Advances in fabrication technology have enabled modularizing electronic components at the micro- or nano-scale and composing these modules on demand into larger circuits. Micromodular and nanomodular electronics (ME and NE) open a new design space in electronics, promising a degree of flexibility, extensibility, and accessibility far superior to traditional monolithic methods. ME/NE leverage a multi-stage process of initial imprecise component deposition, followed by precise wire printing to compose them into a circuit. Due to imperfections in deposition, each circuit instance has a unique layout with its own component placement and wire routing solutions, putting the design automation process on the critical path. Moreover, high-performance nanomodular components enable the synthesis of larger heterogeneous circuits than traditional printed electronics, requiring more scalable algorithms. ME/NE thus introduce a tradeoff between the time-to-solution for placement/routing algorithms and the resulting total wire length, with the latter dictating circuit printing time. We explore this tradeoff by adapting standard partitioning, floorplanning, placement, and routing algorithms to the unique characteristics of ME/NE. Our evaluations demonstrate significant optimization headroom in different dimensions. For example, our tunable algorithms can deliver a $108\times$ improvement in end-to-end manufacturing time at the cost of $21\%$ increase in total wire length. Conversely, circuit quality/performance can be prioritized at the cost of increased manufacturing time, highlighting the value of the ability to dynamically navigate the tradeoff space according to the primary optimization metric.