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Bounds on Atomistic Disorder for Scalable Electron Shuttling

Raphaël J. Prentki, Pericles Philippopoulos, Mohammad Reza Mostaan, Félix Beaudoin

Abstract

Electron shuttling is emerging as a key enabler of scalable silicon spin-qubit quantum computing, but fidelities are limited by atomistic disorder. We introduce a multiscale simulation framework combining time-dependent finite-element electrostatics and atomistic tight-binding to capture the impact of random alloying and interface roughness on the valley splitting and phase of shuttled electrons. We find that shuttling fidelities are strongly suppressed by interface roughness, with a sharp anomaly near the atomic-layer scale, setting quantitative guidelines to realize scalable shuttling.

Bounds on Atomistic Disorder for Scalable Electron Shuttling

Abstract

Electron shuttling is emerging as a key enabler of scalable silicon spin-qubit quantum computing, but fidelities are limited by atomistic disorder. We introduce a multiscale simulation framework combining time-dependent finite-element electrostatics and atomistic tight-binding to capture the impact of random alloying and interface roughness on the valley splitting and phase of shuttled electrons. We find that shuttling fidelities are strongly suppressed by interface roughness, with a sharp anomaly near the atomic-layer scale, setting quantitative guidelines to realize scalable shuttling.

Paper Structure

This paper contains 9 equations, 5 figures.

Figures (5)

  • Figure 1: Schematic of the simulated CB device, which models the "QuBus" of Ref. seidler2022conveyor (not to scale). The clavier gates ($V_{1,2,3,4}$) are 60nm wide and separated by 10nm gaps. The finite-element simulations cover the structure shown in its entirety, while the atomistic simulations are restricted to the region inside the dashed lines.
  • Figure 2: Rough Si--SiGe interface with RMS height of 3. Purple (white) spheres denote Si (Ge) atoms. The Si and SiGe layers are vertically offset for clarity.
  • Figure 3: Snapshots of the shuttled electron ground state probability density, $|\psi_0(\mathbf{r},t_{p})|^2$ for $p\in\{1,2,\ldots,18\}$, overlaid onto a slice of the simulated CB atomic structure, for a system with rough Si--SiGe interface RMS height of 2. The slice contains the three atomic layers closest to the $y=0$ plane and spans the full length of simulated CB, from $x=0$ to $x=L$. Each sphere represents an atom. Ge atoms are shown in white. The color of each Si atom encodes the probability of finding the electron on that atom.
  • Figure 4: Time-dependent (a) valley splitting and (b) valley phase of CBs with rough Si--SiGe interface RMS heights ranging from $0$ to $10\angstrom$. Time is normalized by the period $T$ of the clavier gate voltages [Eq. \ref{['eq:V1234']}]. Diamonds represent the results of TB simulations, while curves are piecewise cubic Hermite interpolating polynomial fits to the data.
  • Figure 5: Shuttling infidelity due to leakage into the valley-excited state for electrons shuttled in CBs with rough Si--SiGe interface RMS heights ranging from $0$ to $10\angstrom$. The shaded areas indicate the variability of the infidelity, corresponding to $\pm 1$ standard deviation computed from ensembles of CB atomic structures.