A Resource-Driven Approach for Implementing CNNs on FPGAs Using Adaptive IPs
Philippe Magalhães, Virginie Fresse, Benoît Suffran, Olivier Alata
TL;DR
This paper tackles real-time CNN deployment on resource-constrained FPGAs by introducing a library of four resource-adaptive convolution IPs implemented in VHDL with fixed-point arithmetic. The IPs serially load kernel coefficients while consuming varying amounts of DSPs, logic, and parallelism to fit different resource budgets. An experimental evaluation on a Zynq UltraScale+ platform demonstrates clear resource-performance trade-offs and confirms timing feasibility without routing congestion, while comparisons indicate hardware-independent adaptability. The work enables flexible, energy-efficient CNN acceleration across diverse FPGA configurations and suggests future expansion to pooling and activation layers and automatic IP selection. The practical impact lies in providing a scalable, architecture-agnostic framework for incorporating CNNs into edge devices and embedded systems.
Abstract
The increasing demand for real-time, low-latency artificial intelligence applications has propelled the use of Field-Programmable Gate Arrays (FPGAs) for Convolutional Neural Network (CNN) implementations. FPGAs offer reconfigurability, energy efficiency, and performance advantages over GPUs, making them suitable for edge devices and embedded systems. This work presents a novel library of resource-efficient convolution IPs designed to automatically adapt to the available FPGA resources. Developed in VHDL, these IPs are parameterizable and utilize fixed-point arithmetic for optimal performance. Four IPs are introduced, each tailored to specific resource constraints, offering flexibility in DSP usage, logic consumption, and precision. Experimental results on a Zynq UltraScale+ FPGA highlight the trade-offs between performance and resource usage. The comparison with recent FPGA-based CNN acceleration techniques emphasizes the versatility and independence of this approach from specific FPGA architectures or technological advancements. Future work will expand the library to include pooling and activation functions, enabling broader applicability and integration into CNN frameworks.
