Pretraining with hierarchical memories: separating long-tail and common knowledge
Hadi Pouransari, David Grangier, C Thomas, Michael Kirchhof, Oncel Tuzel
TL;DR
The paper tackles inefficiencies in storing world knowledge solely in model parameters by introducing hierarchical parametric memories that separate long-tail knowledge from common knowledge. It couples a small anchor transformer with a large, hierarchically organized memory bank retrieved by a clustering-based memory retriever, enabling context-dependent memory augmentation during pretraining and inference. FFN-Memories emerge as the most effective memory type, with deeper, larger memory banks yielding robust gains across CK and SK tasks, achieving performance comparable to larger models while using fewer runtime parameters. The approach demonstrates practical benefits for on-device deployment, privacy, and post-hoc memory augmentation, and it shows complementary potential when combined with retrieval-augmented generation (RAG).
Abstract
The impressive performance gains of modern language models currently rely on scaling parameters: larger models store more world knowledge and reason better. Yet compressing all world knowledge into parameters is unnecessary, as only a fraction is used per prompt, and impractical for edge devices with limited inference-time memory and compute. We address this shortcoming by a memory-augmented architecture and a pretraining strategy aligned with existing hardware paradigms. We introduce small language models that access large hierarchical parametric memory banks encoding world knowledge. During pretraining and inference, we fetch a small, context-dependent memory block and add it to the model. Our pretraining learns to store long-tail world knowledge in the memory parameters, while the small language model acts as an anchor capturing common knowledge and general reasoning abilities. Through trillion-token-scale experiments, we show significant gains: a 160M-parameters model augmented with an 18M-parameters memory fetched from a 4.6B memory bank obtains comparable performance to a regular model with more than 2x the parameters. Through extensive experiments, we study the optimal type and size of parametric memories in transformers, scaling them to over 21B parameters. We find that our proposed hierarchical feed-forward memories work robustly across transformer architectures, whether added during pretraining or post-hoc.
