Programming RISC-V accelerators via Fortran

TL;DR

The work addresses running Fortran HPC codes on emerging RISC-V PCIe accelerators without rewriting code. It leverages MLIR and Flang by lowering Flang's FIR/HLFIR into standard MLIR dialects to access a rich set of compiler transformations and targets. A backend strategy with host and device dialects is developed to map to accelerator APIs, enabling code generation and runtime integration, including a printer that emits C++ for device calls. A Tenstorrent Tensix-based case study with an OpenMP target-offload SAXPY example demonstrates practical porting and energy-efficient performance benefits, illustrating the feasibility and portability of this approach.

Abstract

A range of RISC-V based accelerators are available and coming to market, and there is strong potential for these to be used for High Performance Computing (HPC) workloads. However, such accelerators tend to provide bespoke programming models and APIs that require codes to be rewritten. In scientific computing, where many of the simulation code are highly complex, extensive, and written in Fortran, this is not realistic. In this extended abstract we present an approach that enables driving such architectures via Fortran, avoiding code redevelopment.

Figures (1)

• Figure 1: Illustration of our approach lowering Flang to target RISC-V accelerators