Parallelism Empowered Guessing Random Additive Noise Decoding
Li Wan, Huarui Yin, Wenyi Zhang
TL;DR
The paper tackles the challenge of achieving ML decoding with GRAND while leveraging hardware parallelism. It introduces the EP tree to unify error pattern representations and enable parallel exploration, delivering a parallel SGRAND that preserves ML and a suite of acceleration techniques (pruning, tree-based computation, early termination). It further enhances ORBGRAND by integrating the EP-tree framework into a hybrid method that attains ML-like performance with minimal overhead. Simulation results show substantial latency reductions, with 3.75× speedup for parallel SGRAND and up to 4.8× for the hybrid enhanced ORBGRAND, highlighting practical potential for URLLC and other latency-constrained settings. The work lays a path toward hardware-realizable, universal decoders that combine ML optimality with scalable parallelism.
Abstract
Advances in parallel hardware platforms have motivated the development of efficient universal decoders capable of meeting stringent throughput and latency requirements. Guessing Random Additive Noise Decoding (GRAND) is a recently proposed decoding paradigm that sequentially tests Error Patterns (EPs) until finding a valid codeword. While Soft GRAND (SGRAND) achieves maximum-likelihood (ML) decoding, its inherently sequential nature hinders parallelism and results in high decoding latency. In this work, we utilize a unified binary tree representation of EPs, termed the EP tree, which enables compact representation, efficient manipulation, and parallel exploration. Building upon this EP tree representation, we propose a parallel design of SGRAND, preserving its ML optimality while significantly reducing decoding latency through pruning strategies and tree-based computation. Furthermore, we develop a hybrid GRAND algorithm that enhances Ordered Reliability Bits (ORB) GRAND with the EP tree representation, thereby achieving ML decoding with minimal additional computational cost beyond ORBGRAND while retaining parallel efficiency. Numerical experiments demonstrate that parallel SGRAND achieves a $3.75\times$ acceleration compared to serial implementation, while the hybrid enhanced method achieves a $4.8\times$ acceleration, with further gains expected under hardware mapping.
