Accurate Small-Signal Modeling of Digitally Controlled Buck Converters with ADC-PWM Synchronization

TL;DR

This work addresses the accuracy gaps of conventional small-signal models for digitally controlled buck converters by incorporating DPWM-ADC synchronization, which induces sampling-sideband coupling. It introduces an exact sampled-data framework that yields a closed-form digital loop gain $T_{pul}(z)=G_{Plant}(z)G_C(z)$ and a linked analog gain $T_i(s)=G_{CM}(s)G_{id}(s)H_i$, with synchronization captured by $H_{sync}(z)$ and a sampling delay $T_D$. The approach covers both asymmetrical and symmetrical carrier schemes, using a modified $\mathcal{Z}_m$ transform to map delays into the digital domain and enabling straightforward compensator design. Extensive simulations and experimental results validate the model across operating modes, demonstrating high accuracy and practical utility for digital control of buck converters.

Abstract

Digital control has become increasingly widespread in modern power electronic converters. When acquiring feedback signals such as the inductor current, synchronizing the analog-to-digital converter (ADC) with the digital pulse-width modulator (DPWM) is commonly employed to accurately track their steady-state average. However, the small-signal implications of such synchronization have not been investigated. This paper presents an exact small-signal model for digitally controlled buck converters operating in forced continuous-conduction mode (FCCM) under constant-frequency current-mode control, explicitly accounting for DPWM-ADC synchronization. Using a sampled-data framework, the proposed model captures all sideband effects introduced by the sampling process, yielding precise predictions of both analog and digital loop gains, even at frequencies beyond the switching and sampling frequencies. Both asymmetrical and symmetrical carrier modulations are considered. Furthermore, the digital loop gain is derived in closed form using the modified z-transform, enabling low-complexity compensator design and stability assessment. Within this framework, the analog loop gain can be directly obtained from the digital loop gain, thereby eliminating the need for computationally intensive infinite series evaluations. The validity of the proposed model is confirmed through both simulation and experimental results.

Figures (14)

• Figure 1: PWM modulation schemes with possible synchronized ADC sampling instants (Green) and modulating edges (Red) highlighted. (a) TEM, up-counting sawtooth carrier. (b) LEM, down-counting sawtooth carrier. (c) Symmetrical modulation, triangular carrier.
• Figure 2: A digital buck with ADC sampling at the center of the PWM On-interval and synchronized to the TEM DPWM.
• Figure 3: Key discrete-domain waveforms of the TEM digital buck converter, the vertical dashed brown line marks the steady-state ADC sampling instant, the vertical dashed green line indicates the ADC sampling instant under perturbation.
• Figure 4: Sampling instant variation due to DPWM-ADC synchronization. Brown and green vertical dashed lines represent sampling points under steady-state and perturbed, respectively.
• Figure 5: Block diagram of TEM digital buck without ZOH.