Graph Neural Network Acceleration on FPGAs for Fast Inference in Future Muon Triggers at HL-LHC

TL;DR

The paper addresses the challenge of designing fast, reliable muon triggers for HL-LHC under high pileup by comparing CNN and GNN architectures implemented on FPGAs. It benchmarks these models on an idealized ATLAS Muon Spectrometer Phase II geometry with a large simulated dataset, focusing on latency targets of $O(100\\,\\mathrm{ns})$ and sub-$250\\,\\mathrm{ns}$ for the CNN. The CNN demonstrates feasibility of image based inference on FPGAs with high leading-muon efficiency ($p_T>14\\,\\mathrm{GeV}$) and low background, while the GNN achieves competitive single-track efficiency with a sharper turn-on and is naturally suited to multi-track extensions due to explicit connectivity. The results indicate that GNNs are a promising path for future multi-muon triggers and motivate continued hardware deployment work including latency validation and dataset expansion.

Abstract

The High-Luminosity LHC (HL-LHC) will reach luminosities up to 7 times higher than the previous run, yielding denser events and larger occupancies. Next generation trigger algorithms must retain reliable selection within a strict latency budget. This work explores machine-learning approaches for future muon triggers, using the ATLAS Muon Spectrometer as a benchmark. A Convolutional Neural Network (CNN) is used as a reference, while a Graph Neural Network (GNN) is introduced as a natural model for sparse detector data. Preliminary single-track studies show that GNNs achieve high efficiency with compact architectures, an encouraging result in view of FPGA deployment.

Figures (1)

• Figure 1: Efficiency turn-on curves: CNN (leading and subleading) vs. preliminary GNN results (single-track).