Robust NbN on Si-SiGe hybrid superconducting-semiconducting microwave quantum circuit

Abstract

Advancing large-scale quantum computing requires superconducting circuits that combine long coherence times with compatibility with semiconductor technology. We investigate niobium nitride (NbN) coplanar waveguide resonators integrated with Si/SiGe quantum wells, creating a hybrid platform designed for CMOS-compatible quantum hardware. Using temperature-dependent microwave spectroscopy in the single-photon regime, we examine resonance frequency and quality factor variations to probe the underlying loss mechanisms. Our analysis identifies the roles of two-level systems, quasiparticles, and scattering processes, and connects these losses to wafer properties and fabrication methods. The devices demonstrate reproducible performance and stable operation maintained for over two years, highlighting their robustness. These results provide design guidelines for developing low-loss, CMOS-compatible superconducting circuits and support progress toward resilient, scalable architectures for quantum information processing.

Figures (11)

• Figure 1: (a) False colour SEM image of fabricated SiGe chip. (b,c) Surface current density magnitude $J_{s}$ (A/m) for the first and second resonant modes, respectively, obtained from Sonnet simulations. (d) NbN-Si/SiGe CPW resonator step-by-step fabrication process, from left to right, includes: NbN sputtering, superconducting film etch, and SiGe buffer layer etch. (e) The AFM line profile of NbN CPW resonator fabricated on the Si/SiGe wafer.
• Figure 2: (a) Schematic of the SiGe wafer with sputtered NbN top layer. (b) Low-resolution cross-sectional STEM images of the wafer. (c) HAADF images of the Si constraint quantum well layer between the Si/SiGe buffer layer. (d) High-resolution HAADF images between n-doped layer Si$_{0.7}$Ge$_{0.3}$, the Si cap layer, and the sputtered NbN layer. The scale bar is 5 nm. (e) Elemental map of this area, including Ge, Nb, O, and Si.
• Figure 3: Measured (red) and fitted (black) data of notch-type circuit model for (a) $|$S$_{21}|$ (dB), (b) $\langle$ S$_{21}$, and (c) parametric plot at P$_{in}$ = -115 dBm. (d) $|$S$_{21}|$ (dB) and (e) $\langle$ S$_{21}$ at $f_{r1,s1}$ = 5.04 GHz, with the power range -140 dBm $<$ P$_{in}$$<$ -115 dBm at $T$ = 50 mK. All data are extracted from S1 at $3^{rd}$ measurements.
• Figure 4: Measured $Q_i$ (a), $Q_c$ (b) and $Q_l$ (c) at the fundamental frequency for both chips in the four different cooldowns.
• Figure 5: Measured frequency spectrum (a) and phase (b) for the temperature range between $T$ = 150 mK to 1700 mK with 100 mK step at $P_{in}$ = -115 dBm. Data are extracted from S1 at $2^{nd}$ measurements.