EEsizer: LLM-Based AI Agent for Sizing of Analog and Mixed Signal Circuit

TL;DR

AMS circuit sizing is a challenging, high-dimensional problem due to trade-offs among performance, power, and area. The authors propose EEsizer, an LLM-based AI agent that integrates large language models with circuit simulators in a closed-loop ReAct/Chain-of-Thought framework to autonomously optimize transistor sizes. They benchmark eight LLMs and demonstrate node-transfer sizing from 180 nm to 90 nm, achieving robust op-amp performance and showing that larger models (notably OpenAI o3) provide the most reliable convergence at advanced nodes, while also performing variation analysis. The work highlights the potential of LLM-driven automation for AMS design without domain-specific fine-tuning, and it provides a publicly released implementation for broader adoption. Overall, EEsizer enables automated, adaptable transistor sizing across technology nodes with minimal human intervention.

Abstract

The design of Analog and Mixed-Signal (AMS) integrated circuits (ICs) often involves significant manual effort, especially during the transistor sizing process. While Machine Learning techniques in Electronic Design Automation (EDA) have shown promise in reducing complexity and minimizing human intervention, they still face challenges such as numerous iterations and a lack of knowledge about AMS circuit design. Recently, Large Language Models (LLMs) have demonstrated significant potential across various fields, showing a certain level of knowledge in circuit design and indicating their potential to automate the transistor sizing process. In this work, we propose EEsizer, an LLM-based AI agent that integrates large language models with circuit simulators and custom data analysis functions, enabling fully automated, closed-loop transistor sizing without relying on external knowledge. By employing prompt engineering and Chain-of-Thought reasoning, the agent iteratively explores design directions, evaluates performance, and refines solutions with minimal human intervention. We first benchmarked 8 LLMs on six basic circuits and selected three high-performing models to optimize a 20-transistor CMOS operational amplifier, targeting multiple performance metrics, including rail-to-rail operation from 180 nm to 90 nm technology nodes. Notably, OpenAI o3 successfully achieved the user-intended target at 90 nm across three different test groups, with a maximum of 20 iterations, demonstrating adaptability and robustness at advanced nodes. To assess design robustness, we manually designed a bias circuit and performed a variation analysis using Gaussian-distributed variations on transistor dimensions and threshold voltages.

Figures (14)

• Figure 1: A typical circuit design flow. The process begins with front-end stages including topology selection and circuit sizing, followed by back-end tasks such as placement, routing, and post-layout simulation. The results from post-layout simulation often necessitate adjustments to the circuit sizing.
• Figure 2: The entire process for circuit sizing with EEsizer. The process begins with the task decomposition stage, generating four tasks for different stages. Action, observation and comparison formed a ReAct optimization loop. Finally, the agent generates output consisting of reasons for changes and modifications of the netlist for the user.
• Figure 3: Example of user input consisting of a SPICE netlist that defines the circuit structure, devices, connections, and initial sizing values, and a set of target performance metrics provided by the user, including gain, bandwidth, and phase margin. These two components are the only required inputs for EEsizer.
• Figure 4: Chain-of-Thought (CoT) guided optimization framework, in which the circuit type, target performance, current results, and historical results, generated by LLMs, are integrated into the context (highlighted in blue), while the underlying template remains in black.
• Figure 5: An example of LLM response for the CoT prompt.