Fault Injection in On-Chip Interconnects: A Comparative Study of Wishbone, AXI-Lite, and AXI

TL;DR

This paper tackles the vulnerability of on-chip interconnect buses to fault injection attacks across three common protocols: Wishbone, AXI-Lite, and AXI. It employs simulation-driven fault campaigns using four fault models to map outcomes to targeted registers and timing windows. The analysis reveals both shared and protocol-specific weaknesses, with simple faults more effective on Wishbone and richer attack surfaces emerging on AXI-Lite and AXI, especially in state and handshake logic. Practical guidelines—such as hardening handshake paths, protecting control registers, and using mux-based selection to mitigate data multireads—offer actionable steps for resilient SoC interconnect design.

Abstract

Fault injection attacks exploit physical disturbances to compromise the functionality and security of integrated circuits. As System on Chip (SoC) architectures grow in complexity, the vulnerability of on chip communication fabrics has become increasingly prominent. Buses, serving as interconnects among various IP cores, represent potential vectors for fault-based exploitation. In this study, we perform simulation-driven fault injection across three mainstream bus protocols Wishbone, AXI Lite, and AXI. We systematically examine fault success rates, spatial vulnerability distributions, and timing dependencies to characterize how faults interact with bus-level transactions. The results uncover consistent behavioral patterns across protocols, offering practical insights for both attack modeling and the development of resilient SoC designs.