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Programmable Photonic Circuit for Optical Logic Operations and 2-Bit Decoding

Noel Francisco Prado Bucaro, Yushan Hu, Satoshi Sunada, Takeo Maruyama

Abstract

We present a programmable silicon photonic circuit composed of cascaded multiport directional couplers interleaved with thermo-optic phase shifters. The device forms a reconfigurable interferometric network capable of realizing arbitrary $N \times N$ unitary transformations. By tuning the phase shifters, the same circuit can be configured to perform both optical logic gates and 2-bit decoding functions. Optimal phase settings are determined through Bayesian optimization. The circuit maintains stable operation across multiple wavelengths with 50 GHz spacing, suggesting potential for wavelength-parallel optical processing. These results highlight a pathway toward programmable and integrated photonic circuits.

Programmable Photonic Circuit for Optical Logic Operations and 2-Bit Decoding

Abstract

We present a programmable silicon photonic circuit composed of cascaded multiport directional couplers interleaved with thermo-optic phase shifters. The device forms a reconfigurable interferometric network capable of realizing arbitrary unitary transformations. By tuning the phase shifters, the same circuit can be configured to perform both optical logic gates and 2-bit decoding functions. Optimal phase settings are determined through Bayesian optimization. The circuit maintains stable operation across multiple wavelengths with 50 GHz spacing, suggesting potential for wavelength-parallel optical processing. These results highlight a pathway toward programmable and integrated photonic circuits.

Paper Structure

This paper contains 11 sections, 3 equations, 6 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Operating Principles
  3. Device Fabrication and Experimental Results
  4. Device Fabrication
  5. Device Characterization
  6. Optimization Method
  7. Experimental Setup
  8. Results
  9. Optical Logic Gates
  10. 2-Bit Decoder
  11. Conclusions

Figures (6)

  • Figure 1: Design and Implementation of the Programmable Photonic Circuit. (a) Schematic architecture of the cascaded photonic mesh. The circuit consists of repeating stages of multiport directional couplers (MDCs) interleaved by thermo-optic phase shifters. The lower inset details the directional coupler geometry, defined by the interaction length (L), waveguide gap (G), and width (W). (b) Micrograph of the fabricated device region corresponding to the highlighted box in (a). The thermo-optic phase shifter pads (yellow) are positioned over the silicon waveguides to enable localized phase tuning. (c) Photograph of the fully packaged system. The photonic integrated circuit (PIC) is wire-bonded to a custom printed circuit board (PCB) to provide electronic control signals to the 56 integrated heaters.
  • Figure 2: Dynamic response of the optical logic gate. (a) Time-domain traces showing the output following the input logic states (AND gate configuration). (b) Detailed view of the switching transient, showing a 10--90% rise time of approximately 110 $\mu$s, characteristic of the thermo-optic effect.
  • Figure 3: Experimental setup used for optical logic gate and decoder measurements with closed-loop control.
  • Figure 4: Measured output intensities for six optical logic gates under optimized heaters configuration.
  • Figure 5: Extinction ratio of the optical logic gates measured across multiple wavelengths with 50 GHz spacing.
  • ...and 1 more figures