The Cream Rises to the Top: Efficient Reranking Method for Verilog Code Generation

TL;DR

This work addresses the challenge of generating reliable Verilog code with large language models by reframing code generation as a semantic alignment task between specifications and implementations. It introduces VCD-Rnk, a lightweight discriminative reranker built via collaborative dual-teacher distillation to produce VerilogJudge-47K and fine-tunes a downstream model with LoRA, enabling efficient reranking without test execution. Empirically, VCD-Rnk yields substantial gains in pass@1 across RTLLM-v1.1 and ResBench and approaches a large fraction of the theoretical upper bound while delivering significantly lower runtime overhead than test-based baselines. The approach holds promise for extending to other HDL families and hardware design tasks, offering a practical path to trustworthy, single-solution Verilog generation.

Abstract

LLMs face significant challenges in Verilog generation due to limited domain-specific knowledge. While sampling techniques improve pass@k metrics, hardware engineers need one trustworthy solution rather than uncertain candidates. To bridge this gap, we formulate it as a semantic alignment problem between requirements and Verilog implementations, and propose VCD-RNK, a discriminator model tailored for efficient Verilog code reranking. Specifically, VCD-RNKincorporates Verilog-specific reasoning by distilling expert knowledge across three dimensions: code semantic analysis, test case generation, and functional correctness assessment. By explicitly simulating the above reasoning processes during inference, VCD-RNK effectively avoids computationally intensive test execution in existing methods.

Figures (4)

• Figure 1: Performance on ResBench benchmark.
• Figure 2: Comparison of existing methods and VCD-Rnk.
• Figure 3: Overview of our method.
• Figure 4: Ablation results on ResBench.