Bridging Simulation and Silicon: A Study of RISC-V Hardware and FireSim Simulation

TL;DR

This work directly tackles the fidelity gap between FireSim-based RISC-V simulations and real hardware by modeling Banana Pi and MILK-V platforms in FireSim and validating with microbenchmarks plus HPC workloads. Using Rocket in-order and BOOM out-of-order cores tuned via MicroBench, NAS, UME, and Lammps, the authors quantify correlations through relative speedups and identify persistent deviations driven by memory subsystem differences and limited vendor details. The key contributions include a systematic methodology for matching FireSim configurations to commodity RISC-V hardware, a detailed assessment of where FireSim predicts performance well and where it falls short, and a public dataset of runtimes to support future benchmarking. The findings underscore FireSim’s value for architectural trend analysis and exploration while highlighting practical limitations in achieving cycle-level accuracy without more detailed hardware specifications and richer memory modeling.

Abstract

RISC-V ISA-based processors have recently emerged as both powerful and energy-efficient computing platforms. The release of the MILK-V Pioneer marked a significant milestone as the first desktop-grade RISC-V system. With increasing engagement from both academia and industry, such platforms exhibit strong potential for adoption in high-performance computing (HPC) environments. The open-source, FPGA-accelerated FireSim framework has emerged as a flexible and scalable tool for architectural exploration, enabling simulation of various system configurations using RISC-V cores. Despite its capabilities, there remains a lack of systematic evaluation regarding the feasibility and performance prediction accuracy of FireSim when compared to physical hardware. In this study, we address this gap by modeling a commercially available single-board computer and a desktop-grade RISC-V CPU within FireSim. To ensure fidelity between simulation and real hardware, we first measure the performance of a series of benchmarks to compare runtime behavior under single-core and four-core configurations. Based on the closest matching simulation parameters, we subsequently evaluate performance using a representative mini-application and the LAMMPS molecular dynamics code. Our findings indicate that while FireSim provides valuable insights into architectural performance trends, discrepancies remain between simulated and measured runtimes. These deviations stem from both inherent limitations of the simulation environment and the restricted availability of detailed performance specifications from CPU manufacturers, which hinder precise configuration matching.

Figures (7)

• Figure 1: Microbenchmark performance on FireSim tuned Rocket core to match the Banana Pi hardware, labeled as the Banana Pi Sim Model (See Table \ref{['tab:arch_spec']}), normalized by the Banana Pi hardware performance results. Fast Banana Pi Sim Model results have also been included to study the effects of increasing the clock rate by a factor of $2$ up to $3.2$GHz.
• Figure 2: Microbenchmark performance on FireSim of Small, Medium, and Large BOOM cores and a tuned Large BOOM core to match the MILK-V hardware (MILK-V Sim Model, See Table \ref{['tab:arch_spec']}), normalized by the MILK-V hardware performance.
• Figure 3: Relative speedup of NAS Parallel Benchmarks on FireSim (Rocket cores) compared to Banana Pi hardware (target value = 1.0; lower deviation indicates closer performance match).
• Figure 4: Relative speedup of NAS Parallel Benchmarks on FireSim (BOOM cores) compared to MILK-V hardware (target value = 1.0).
• Figure 5: Relative speedup of UME on FireSim compared to actual hardware. Here Rocket-based Banana Pi Sim model is compared with Banana Pi hardware and BOOM-based MILK-V model is compared with MILK-V hardware.