Photonic Matrix Multiplication Circuit Based on Double Racetrack Resonator Building Blocks

TL;DR

This work presents a programmable photonic matrix multiplication framework built from double racetrack (DRT) resonators. By deriving the DRT transfer function and showing its close resemblance to traditional building blocks, the authors enable a nulling-based synthesis to realize arbitrary unitary matrices, demonstrated on a 3×3 processor with high fidelity validated by full-vector FEM and hybrid FEM-circuit modelling. They also show the framework’s versatility by mapping a non-unitary low-pass filter via unitary recovery, confirming applicability to broader optical signal processing tasks. While offering compact, tunable spectral control, the approach exhibits scalability challenges as matrix size grows, motivating further optimization for large-scale reconfigurable photonic circuits and integration with microwave photonics for emerging telecom technologies.

Abstract

This paper presents a novel design framework for photonic matrix multiplication based on programmable photonic integrated circuits using double racetrack (DRT) resonators as building blocks. Here, we analytically demonstrate that the transfer function of the DRT resonator building block resembles that conventional building blocks, such as directional couplers and MZI, making it suitable for building programmable circuits that handle complex matrix calculations. Using this new DRT resonators building block, a 3-by-3 photonic processor is implemented and validated through full-wave Finite Element Method (FEM) simulations, and scalability is further analysed using hybrid FEM-circuit modelling. Additionally, we implement a low-pass filter as a non-unitary system example, showcasing the flexibility of the approach. Results confirm high fidelity between simulated and analytical models, supporting the viability of DRT resonators for reconfigurable photonic circuits. We believe that the proposed DRT resonator building blocks have the potential to complement and integrate with other previously reported blocks, thereby enhancing the fidelity and expanding the application scope of programmable photonic integrated circuits, particularly for all-optical signal processing in communication systems and for integration within microwave photonics platforms targeting emerging telecommunications technologies.

Figures (6)

• Figure 1: (a) Physical layout of DRT resonator building block. (b) Equivalent circuit model.
• Figure 2: (a) An example of 4-by-4 PIC with required building blocks and output phase shifts $\phi_o$. (b) DRT geometry layout and its design parameters. (c) Spectrum of the magnitude of the bar transmission $|t_{11}|^2$ and cross transmission $|t_{21}|^2$, for $\Delta n_{1,2,3}=0$. (d) Spectrum $|t_{11}|^2$ and $|t_{21}|^2$ as a function of $\Delta n_2$ of the arcs of DRT. (e) Phase shift $\phi$ as a function of $\Delta n_1$ or $\Delta n_3$.
• Figure 3: (a) Schematic of the practical realisation of the 3-by-3 unitary matrix. Coupling parameter $K$ and external phase shift $\phi$ for each building block are calculated as in Section \ref{['framework']}. (b) Schematic of the 3-by-3 photonic circuit where phase shift $\phi$ are realised by tuning $\Delta n_1$ and the coupling constant $K$ is realised by tuning $\Delta n_2$. (c–e) Full-wave 3D simulation of the designed 3-by-3 photonic circuit when (c) $I_1$ is on, (d) $I_2$ is on, and (e) $I_3$ is on. (f-h) The transmission parameters $\mathcal{T}_{i,j}$ are entries of $\mathcal{T}$ as a function of frequency (wavelength), where $i,j$ are the output and input ports.
• Figure 4: Normalised Square Error (NSE) as a function of frequency for the example 3-by-3 photonic integrated circuit.
• Figure 5: (a) NSE vs different sizes of PIC using DRT building blocks. (b) NSE vs different sizes of PIC using DC building blocks Talib2025.