Benchmarking Single-Qubit Gates on a Neutral Atom Quantum Processor

Abstract

We present benchmarking results for single-qubit gates implemented on a neutral atom quantum processor using Direct Randomized Benchmarking (DRB) and Gate Set Tomography (GST). The DRB protocol involves preparing stabilizer states, applying $m$ layers of native single-qubit gates, and measuring in the computational basis, providing an efficient error characterization under a stochastic Pauli noise model. GST enables the full, self-consistent reconstruction of quantum processes, including gates, input states, and measurements. Both protocols provide robust to state preparation and measurement (SPAM) errors estimations of gate performance, offering complementary perspectives on quantum gate fidelity. For single-qubit gates, DRB yields an average fidelity of $99.963 \%$. The protocol was further applied to a 25-qubit array under global single-qubit control. GST results are consistent with those obtained via DRB. We also introduce a gauge optimization procedure for GST that brings the reconstructed gates, input states, and measurements into a canonical frame, enabling meaningful fidelity comparisons while preserving physical constraints. These constraints of the operators -- such as complete positivity and trace preservation -- are enforced by performing the optimization over the Stiefel manifold. The combined analysis supports the use of complementary benchmarking techniques for characterizing scalable quantum architectures.

Figures (8)

• Figure 1: A DRB circuit in the single-qubit case is composed as follows. The processes $G_I$ and $G_M$ correspond to stabilizer state preparation and stabilizer measurement, respectively. The superoperators $G_1, G_2, \ldots, G_m$ represent randomly generated generators of the Clifford group. $K$ represents the number of randomized circuits with depyh $m$.
• Figure 2: (a)–(c) GST circuits. The quantum process under investigation is denoted as $G_0$, while $G_1$ and $G_2$ represent the superoperators corresponding to state preparation and measurement, respectively. $G_1$ and $G_2$ are incorporated into the circuits as $G_k$. In the final set of circuits, the process under investigation is the identity (trivial) operation. (d) Additional circuits used in long-sequence GST. Here, $g$ denotes a germ, which is a sequence composed of gates from the gate set, and $p$ corresponds to the number of repetitions of the germ $g$ within the circuit.
• Figure 3: (a) Simulated success probability $P$ as a function of circuit depth $m$ for $T_2 = 600~\mu\text{s}$. Results for outcomes $\ket{0}$ and $\ket{1}$ are shown separately to highlight the impact of SPAM asymmetry. The shaded region indicates statistical spread across all circuits. Error bars demonstrate only the size of these regions. (b) Average gate fidelity $F^{\text{avg}}_{RB}$ estimated from DRB simulation (solid line with $95\%$ confidence interval error bars) compared to theoretical predictions based on superoperator analysis (dashed line). Good agreement is observed, with small deviations for short $T_2$ reflecting the breakdown of DRB assumptions in high-noise regimes.
• Figure 4: Reconstructed superoperators for GST at $T_1 = 100~\text{ms}, T_2 = 600~\mu\text{s}$, and SPAM probabilities $p_{0\rightarrow1} = 1 \%$, $p_{1\rightarrow0} = 25 \%$. The diagrams show: (top center) input state; (top left, top right) POVM elements for $\ket{0}$ and $\ket{1}$; (bottom left, bottom right) superoperators for $R_x(\pi/2)$ and $R_y(\pi/2)$. The numerical reconstructions match the parameters of the simulation with high fidelity.
• Figure 5: Fidelity of $R_x$ and $R_y$ gates reconstructed by GST as a function of transverse relaxation time $T_2$. Simulation results (solid lines with $95\%$ confidence interval error bars) are compared with theoretical predictions (dashed lines). The agreement across a wide range of $T_2$ values confirms the accuracy of GST reconstruction.