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A Fully Analog Implementation of Model Predictive Control with Application to Buck Converters

Simone Pirrera, Lorenzo Calogero, Francesco Gabriele, Diego Regruto, Alessandro Rizzo, Gianluca Setti

TL;DR

This work presents a general method to implement Model Predictive Control as a fully analog circuit by leveraging reduced-complexity Explicit MPC policies expressed as piecewise-affine functions. Four complexity-reduction strategies—Move Blocking, Optimal Region Merging, Hyperplane Separation of Saturated Regions, and Removal of Trivial Inequalities—drastically reduce the EMPC region count, enabling a compact analog hardware realization using a multiplexer, generalized adders, comparators, and a logic network. The method is applied to a DT Buck converter model with disturbance estimation and state estimation, accompanied by a local stability analysis and extensive simulations, including circuit-level LTSpice validation. The results show high-frequency operation (500 kHz switching), fast latency (~1 µs), robust disturbance rejection under wide parameter uncertainty, and favorable comparisons to prior analog and digital MPC approaches, demonstrating practical impact for low-cost, high-speed power electronics control.

Abstract

This paper proposes a novel approach to design analog electronic circuits that implement Model Predictive Control (MPC) policies for dynamical systems described by affine models. Effective approaches to define a reduced-complexity Explicit MPC form are combined and applied to realize an analog circuit comprising a limited set of low-latency, commercially available components. The practical feasibility and effectiveness of the proposed approach are demonstrated through its application in the design of a novel MPC-based controller for DC-DC Buck converters. We formally analyze the stability of the resulting system and conduct extensive numerical simulations to demonstrate the control system's performance in rejecting line and load disturbances.

A Fully Analog Implementation of Model Predictive Control with Application to Buck Converters

TL;DR

This work presents a general method to implement Model Predictive Control as a fully analog circuit by leveraging reduced-complexity Explicit MPC policies expressed as piecewise-affine functions. Four complexity-reduction strategies—Move Blocking, Optimal Region Merging, Hyperplane Separation of Saturated Regions, and Removal of Trivial Inequalities—drastically reduce the EMPC region count, enabling a compact analog hardware realization using a multiplexer, generalized adders, comparators, and a logic network. The method is applied to a DT Buck converter model with disturbance estimation and state estimation, accompanied by a local stability analysis and extensive simulations, including circuit-level LTSpice validation. The results show high-frequency operation (500 kHz switching), fast latency (~1 µs), robust disturbance rejection under wide parameter uncertainty, and favorable comparisons to prior analog and digital MPC approaches, demonstrating practical impact for low-cost, high-speed power electronics control.

Abstract

This paper proposes a novel approach to design analog electronic circuits that implement Model Predictive Control (MPC) policies for dynamical systems described by affine models. Effective approaches to define a reduced-complexity Explicit MPC form are combined and applied to realize an analog circuit comprising a limited set of low-latency, commercially available components. The practical feasibility and effectiveness of the proposed approach are demonstrated through its application in the design of a novel MPC-based controller for DC-DC Buck converters. We formally analyze the stability of the resulting system and conduct extensive numerical simulations to demonstrate the control system's performance in rejecting line and load disturbances.

Paper Structure

This paper contains 35 sections, 7 theorems, 91 equations, 21 figures, 1 table.

Table of Contents

  1. Introduction
  2. Outline
  3. Notation
  4. MPC Problem Formulation
  5. Proposed Design Approach
  6. Reduced-Complexity EMPC Design
  7. Move Blocking Strategy
  8. Optimal Merging of Regions
  9. Hyperplane Separation of Saturated Regions
  10. Removal of Trivial Inequalities
  11. Circuital Implementation
  12. Multiplexer
  13. Generalized Adders
  14. Comparators
  15. Logic Network
  16. ...and 20 more sections

Key Result

Proposition 1

Given Assumption ass:mpc_ref_equil, assume that $x_r$ and $u_r$ satisfy the constraints eq:mpc_op_d, and let $p_k = [x_r^\top, \bm{0}_{n_\nu}^\top]^\top$. Then, problem eq:mpc_qp is uniquely solved by $\hat{u}^* = \bm{1}_{N_p} \otimes u_r$.

Figures (21)

  • Figure 1: EMPC implementation: high-level schematic.
  • Figure 2: Generalized adder for the $i$-th affine function. The blue resistor is used if $K_i^{(+)}< K_i^{(-)}+1$, while the green one is used otherwise.
  • Figure 3: Comparator (case with $n_p = 4$, $\vert{I_p}\vert=2$, and $\vert I_m\vert=3$).
  • Figure 4: Buck converter circuit diagram.
  • Figure 5: Estimator circuit.
  • ...and 16 more figures

Theorems & Definitions (23)

  • Proposition 1
  • proof
  • Proposition 2
  • proof
  • Theorem 1: Explicit MPC paper-bemporad-2002
  • Theorem 2: Affine separation
  • proof
  • Remark 1
  • Remark 2
  • Remark 3
  • ...and 13 more