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Distributed-HISQ: A Distributed Quantum Control Architecture

Yilun Zhao, Kangding Zhao, Peng Zhou, Dingdong Liu, Tingyu Luo, Yuzhen Zheng, Peng Luo, Shun Hu, Jin Lin, Cheng Guo, Yinhe Han, Ying Wang, Mingtang Deng, Junjie Wu, X. Fu

TL;DR

The paper tackles scalability and adaptability in distributed quantum control by addressing cycle level synchronization across controllers and decoupling quantum operation semantics from hardware specifics. It introduces Distributed-HISQ, integrating HISQ a hardware-agnostic quantum control instruction set, with BISP a booking based synchronization protocol, and validates the approach on a commercial superconducting qubit control system. The evaluation shows a runtime reduction of about 22.8 percent and a fidelity improvement of roughly five times compared with lock step schemes, demonstrating the practical impact of near zero overhead synchronization and adaptable control software. Together these contributions provide a viable pathway toward fully scalable distributed quantum control architectures that can accommodate diverse qubit technologies and control electronics.

Abstract

The design of a scalable Quantum Control Architecture (QCA) faces two primary challenges. First, the continuous growth in qubit counts has rendered distributed QCA inevitable, yet the nondeterministic latencies inherent in feedback loops demand cycleaccurate synchronization across multiple controllers. Existing synchronization strategies -- whether lock-step or demand-driven -- introduce significant performance penalties. Second, existing quantum instruction set architectures are polarized, being either too abstract or too granular. This lack of a unifying design necessitates recurrent hardware customization for each new control requirement, which limits the system's reconfigurability and impedes the path toward a scalable and unified digital microarchitecture. Addressing these challenges, we propose Distributed-HISQ, featuring: (i) HISQ, A universal instruction set that redefines quantum control with a hardware-agnostic design. By decoupling from quantum operation semantics, HISQ provides a unified language for control sequences, enabling a single microarchitecture to support various control methods and enhancing system reconfigurability. (ii) BISP, a booking-based synchronization protocol that can potentially achieve zero-cycle synchronization overhead. The feasibility and adaptability of Distributed-HISQ are validated through its implementation on a commercial quantum control system targeting superconducting qubits. We performed a comprehensive evaluation using a customized quantum software stack. Our results show that BISP effectively synchronizes multiple control boards, leading to a 22.8% reduction in average program execution time and a $\sim$5$\times$ reduction in infidelity when compared to an existing lock-step synchronization scheme.

Distributed-HISQ: A Distributed Quantum Control Architecture

TL;DR

The paper tackles scalability and adaptability in distributed quantum control by addressing cycle level synchronization across controllers and decoupling quantum operation semantics from hardware specifics. It introduces Distributed-HISQ, integrating HISQ a hardware-agnostic quantum control instruction set, with BISP a booking based synchronization protocol, and validates the approach on a commercial superconducting qubit control system. The evaluation shows a runtime reduction of about 22.8 percent and a fidelity improvement of roughly five times compared with lock step schemes, demonstrating the practical impact of near zero overhead synchronization and adaptable control software. Together these contributions provide a viable pathway toward fully scalable distributed quantum control architectures that can accommodate diverse qubit technologies and control electronics.

Abstract

The design of a scalable Quantum Control Architecture (QCA) faces two primary challenges. First, the continuous growth in qubit counts has rendered distributed QCA inevitable, yet the nondeterministic latencies inherent in feedback loops demand cycleaccurate synchronization across multiple controllers. Existing synchronization strategies -- whether lock-step or demand-driven -- introduce significant performance penalties. Second, existing quantum instruction set architectures are polarized, being either too abstract or too granular. This lack of a unifying design necessitates recurrent hardware customization for each new control requirement, which limits the system's reconfigurability and impedes the path toward a scalable and unified digital microarchitecture. Addressing these challenges, we propose Distributed-HISQ, featuring: (i) HISQ, A universal instruction set that redefines quantum control with a hardware-agnostic design. By decoupling from quantum operation semantics, HISQ provides a unified language for control sequences, enabling a single microarchitecture to support various control methods and enhancing system reconfigurability. (ii) BISP, a booking-based synchronization protocol that can potentially achieve zero-cycle synchronization overhead. The feasibility and adaptability of Distributed-HISQ are validated through its implementation on a commercial quantum control system targeting superconducting qubits. We performed a comprehensive evaluation using a customized quantum software stack. Our results show that BISP effectively synchronizes multiple control boards, leading to a 22.8% reduction in average program execution time and a 5 reduction in infidelity when compared to an existing lock-step synchronization scheme.

Paper Structure

This paper contains 40 sections, 16 figures, 1 table.

Figures (16)

  • Figure 1: Motivational example of the synchronization challenge. (a) Example circuit slice derived from compiling QFT algorithm running on two quantum chips diadamoDistributedQuantumComputing2021adiskit. (b) OpenQASM crossOpenQASM3Broader2022 code snippets of the highlighted part in the circuit diagram. (c) Inserting a delay instruction into the false branch. (d) Distribute the control flow to other controllers.
  • Figure 2: (a) One implementation of logical $T$ gate relies on the conditional logical $S$ gate. (b) Logical $S$ gate is a sub-circuit with multiple logical operations that take a long execution time.
  • Figure 3: Overview of Distributed-HISQ. (a) Microarchitecture; (b) AWG board and readout board based on HISQ; (c) Single-node architecture; (d) Multi-node architecture;(e) Synchronization scheme.
  • Figure 4: Single-node hardware behavior of BISP. The sync signal is exchanged with a neighbor controller. Upon receiving the signal, the corresponding sync flag (represented by stacked boxes for each neighbor) is set and cleared after being read.
  • Figure 5: Example timing diagrams of nearby (a) and remote (b) synchronization using BISP.
  • ...and 11 more figures