HEEPidermis: a versatile SoC for BioZ recording

TL;DR

HEEPidermis addresses the need for flexible, low-power bioimpedance sensing by integrating programmable current injection, VCO-based ADCs, and on-chip processing into a single open-source SoC. The approach combines a modular digital back-end (X-HEEP) with a tightly integrated analog front-end and an event-driven sub-sampler to enable autonomous, closed-loop BioZ recording and long-term monitoring. Key contributions include two 8-bit iDACs, two VCO-ADC channels, a RISC-V CPU for on-chip feature extraction, and a reusable, open-source platform for system-level simulations and repurposing. The work demonstrates a 65 nm LP tape-out and highlights versatility across GSR and impedance modalities, with potential impact on portable, programmable biomedical sensing.

Abstract

Biological impedance (BioZ) is an information-packed modality that allows for non-invasive monitoring of health and emotional state. Currently, most research involving tissue impedance is based on bulky or fixed-purpose hardware, which limits the scope of research and the possibilities of experiments. In this work, we present HEEPidermis: a System-on-Chip (SoC) which integrates all the blocks needed for tissue impedance measurement, including two 8-bit, arbitrary-signal current DACs, two VCO-based ADCs, and a RISC-V CPU to enable on-chip feature extraction for closed-loop operation. An event-based sub-sampler improves storage and energy efficiency for long-term recording. In addition to the versatile SoC, the digital back-end and behavioral models of the analog front-end are open-source, allowing fast system-level simulations or repurposing. The SoC was taped out on TSMC 65 nm LP process.

Figures (6)

• Figure 1: BioZ measurement using HEEPidermis: a programmable 8-bit current source drains current from tissue, a VCO-based ADC measures voltage drop. Input data is subjected to an event-based comparator to wake up the CPU for processing or adjusting the current to trade off distortion/power.
• Figure 2: (a) System-level overview of the HEEPidermis SoC. The digital back-end is based on the X-HEEP platform. The analog front-end is controlled through memory-mapped registers (in the external peripherals subsystem. (b) Layout of the fabricated chip with overlayed subsystems. (c) Area breakdown among subsystems.
• Figure 3: (a), (b) DNL and INL, respectively, of the iDAC at TT/20 and FF/50 (worse) corner cases.
• Figure 4: VCO-ADC frequency (left) and ADC power (right). The latter is broke down into the oscillator's power (VCO) and the 26 bit counter after it.
• Figure 5: Use case for impedance measurement showing the different stages and blocks involved (top). A behavioral simulation of the process (bottom) for a single VCO for simplicity.