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Towards Deterministic Sub-0.5 us Response on Linux through Interrupt Isolation

Zhouyi Zhou, Zhili Liu, Shancong Zhang, Jiemin Li, Dengke Du, Mengke Sun, Zhiqiang Wang, Hongyan Liu, Guokai Xu

TL;DR

This work tackles the challenge of achieving deterministic Linux latency by mitigating timer interrupts and IPIs through interrupt isolation. It introduces centralized timer handling via an Isolator API and replaces asynchronous IPI signaling with shared-memory communication, allowing dedicated cores to run with minimal interference. Kernel modifications implement per-CPU isolation counters, tick suppression, and deferred maintenance, enabling sub-$0.5 μs$ response times observed in ARM multicore experiments, and sub-microsecond cross-core communication. The results demonstrate a lightweight, practical approach to hard real-time performance on general-purpose OSes, with potential applicability to edge computing, real-time packet processing, and safety-critical embedded systems.

Abstract

Real-time responsiveness in Linux is often constrained by interrupt contention and timer handling overhead, making it challenging to achieve sub-microsecond latency. This work introduces an interrupt isolation approach that centralizes and minimizes timer interrupt interference across CPU cores. By enabling a dedicated API to selectively invoke timer handling routines and suppress non-critical inter-processor interrupts, our design significantly reduces jitter and response latency. Experiments conducted on an ARM-based multicore platform demonstrate that the proposed mechanism consistently achieves sub-0.5 us response times, outperforming conventional Linux PREEMPT-RT configurations. These results highlight the potential of interrupt isolation as a lightweight and effective strategy for deterministic real-time workloads in general-purpose operating systems.

Towards Deterministic Sub-0.5 us Response on Linux through Interrupt Isolation

TL;DR

This work tackles the challenge of achieving deterministic Linux latency by mitigating timer interrupts and IPIs through interrupt isolation. It introduces centralized timer handling via an Isolator API and replaces asynchronous IPI signaling with shared-memory communication, allowing dedicated cores to run with minimal interference. Kernel modifications implement per-CPU isolation counters, tick suppression, and deferred maintenance, enabling sub- response times observed in ARM multicore experiments, and sub-microsecond cross-core communication. The results demonstrate a lightweight, practical approach to hard real-time performance on general-purpose OSes, with potential applicability to edge computing, real-time packet processing, and safety-critical embedded systems.

Abstract

Real-time responsiveness in Linux is often constrained by interrupt contention and timer handling overhead, making it challenging to achieve sub-microsecond latency. This work introduces an interrupt isolation approach that centralizes and minimizes timer interrupt interference across CPU cores. By enabling a dedicated API to selectively invoke timer handling routines and suppress non-critical inter-processor interrupts, our design significantly reduces jitter and response latency. Experiments conducted on an ARM-based multicore platform demonstrate that the proposed mechanism consistently achieves sub-0.5 us response times, outperforming conventional Linux PREEMPT-RT configurations. These results highlight the potential of interrupt isolation as a lightweight and effective strategy for deterministic real-time workloads in general-purpose operating systems.

Paper Structure

This paper contains 35 sections, 1 equation, 12 figures, 3 tables.

Table of Contents

  1. Introduction
  2. Timer Interrupts
  3. Inter-Processor Interrupts (IPIs)
  4. Motivation
  5. Our Approach: Full Isolation via Centralized Timer Handling and Shared-Memory IPI Management
  6. Related Work
  7. Timer Interrupt Control in the Linux Kernel
  8. Inter-Processor Interrupts (IPIs) and Their Effects
  9. CPU Isolation Techniques
  10. Methodology
  11. System Design Overview
  12. Interrupt Suppression and Timer Bypass
  13. Timer Suppression
  14. IPI Suppression and Replacement
  15. Periodic Maintenance
  16. ...and 20 more sections

Figures (12)

  • Figure 1: Core isolation enabling flow and mechanisms.
  • Figure 2: Flowchart for enforcing quiescent state when the isolator counter is active.
  • Figure 3: Flowchart for stopping the per-CPU scheduler timer.
  • Figure 4: Flowchart for purging per-CPU real-time bandwidth timers.
  • Figure 5: System architecture.
  • ...and 7 more figures