Cryogenic performance of field-effect transistors and amplifiers based on selective area grown InAs nanowires

Abstract

Indium-Arsenide (InAs) nanowire field-effect transistors (NWFETs) are promising platforms for high-speed, low-power nanoelectronics operating at cryogenic conditions, relevant for quantum information processing. We use selective area growth (SAG) of nanowires to realize scalable and planar nanowire device geometries that are compatible with standard semiconductor processing techniques. NWFETs are fabricated and their low temperature characteristics - including ION/IOFF ratios, threshold voltages, sub-threshold slope, interfacial trap density, hysteresis, and mobility - are characterized. The NWFETs operate effectively in integrated circuitry relying on saturation-mode operation. In sub-threshold applications such as amplifiers, we find bandwidths exceeding our cryostat wiring, but the gate hysteresis presents challenges for precise tuning of the amplifier operating point. We discuss the role of crystal imperfections and fabrication processes on the transistor characteristics and propose strategies for further improvements.

Figures (3)

• Figure 1: a Schematic illustration of SAG of InAs nanowires. b False-color HAADF STEM micrograph showing the cross-section of a typical nanowire. c False-color SEM micrograph of planar selective area grown nanowire transistors. Each nanowire has individual $\mathrm{Ti}/\mathrm{Au}$ source-drain contacts (yellow) and all devices share a common top gate (pink). d Output characteristics of device D1 at $9$ K with $V_\text{G}$ ranging from $-0.9 \, \mathrm V$ (red) to $1.0 \, \mathrm V$ (blue), in steps of $0.1 \, \mathrm V$. The inset shows a schematic of the device layout.
• Figure 2: a Transfer characteristics of D4 measured at 14 mK for $V_\mathrm{SD}$ ranging from $20 \, \mathrm{mV}$ (red) to $100 \, \mathrm{mV}$ (blue) in steps of 20 mV. b Curves with positive sweep direcition from panel a shown on logarithmic scale. c, d, e, f Bias dependence of the lower bound of the $I_\mathrm{ON}/I_\mathrm{OFF}$ ratio (c), threshold voltage (d), inverse sub-threshold slope and associated density of interfacial charge traps (e), and gate hysteresis (f). g$V_\text{G}$-dependence of the field effect mobility at $V_\mathrm{SD}=20 \, \mathrm{mV}$.
• Figure 3: a Common source amplifier circuit. The selective area grown NWFET (D1) is kept at 7.5 K and the 100 M$\Omega$ load resistor at room temperature. b Amplifier output, $V_\text{out}$, as a function of input, $V_\text{in}$, and bias voltage, $V_\text{DD}$. c Lorentzian fits of the derivative of the curves in panel (b). d Lorentzian's amplitude, $A$ (amplification), and half width, $\gamma$, as a function of bias. e Normalized frequency response of different NWFETs to a sinusoidal $V_\mathrm{G}$ of frequency $f$, measured at $1.2 \, \mathrm K$.