Overhead in Quantum Circuits with Time-Multiplexed Qubit Control

TL;DR

The paper investigates the overhead introduced when time-multiplexing qubit control lines is used to scale quantum processors in cryogenic environments. It shows that two-qubit gate couplers can be grouped on shared drive lines without runtime penalty up to limits set by qubit connectivity (e.g., factor ~4 reduction on square grids, ~3 on heavy-hex layouts), while single-qubit gate serialization introduces an overhead that scales as $T_\Delta(k) \propto \log(k)$, with linear dependence on the number of single-qubit gates $N_1$ and the single-qubit gate duration $t_{1q}$. The study combines numerical simulations and analytical reasoning, including a queueing-theory-based explanation, to benchmark serialization overhead across random circuits and standard quantum algorithms (MQT Bench) on multiple architectures (5×5, 11×11 grids, and IBM Eagle heavy-hex). The results indicate that reduced control lines can be achieved for large-scale quantum computers with only modest increases in circuit duration, suggesting a viable path toward practical scaling. The findings underscore the importance of layout-aware grouping, gate ordering during serialization, and the potential to integrate time multiplexing with other multiplexing strategies to further ease cryogenic wiring challenges while maintaining algorithmic performance.

Abstract

When scaling up quantum processors in a cryogenic environment, it is desirable to limit the number of qubit drive lines going into the cryostat, since fewer lines makes cooling of the system more manageable and the need for complicated electronics setups is reduced. However, although time multiplexing of qubit control enables using just a few drive lines to steer many qubits, it comes with a trade-off: fewer drive lines means fewer qubits can be controlled in parallel, which leads to an overhead in the execution time for quantum algorithms. In this article, we quantify this trade-off through numerical and analytical investigations. For standard quantum processor layouts and typical gate times, we show that the trade-off is favorable for many common quantum algorithms $\unicode{x2014}$ the number of drive lines can be significantly reduced without introducing much overhead. Specifically, we show that couplers for two-qubit gates can be grouped on common drive lines without any overhead up to a limit set by the connectivity of the qubits. For single-qubit gates, we find that the serialization overhead generally scales only logarithmically in the number of qubits sharing a drive line. These results are promising for the continued progress towards large-scale quantum computers.

Figures (21)

• Figure 1: Time-multiplexed qubit control and compilation considerations. (a) A schematic drawing of control-signal demultiplexing via switches to qubits and coupling elements. (b) Layout for a 5$\times$5 square-grid quantum processor with twelve color-coded coupling control groups for two-qubit gates, which minimizes required control lines without increasing the duration of any quantum circuit. (c) Circuit serialization modeling for single-qubit gates: (c1) target circuit and (c2) serialized circuit with controller switch gates Sw (red arrow) and delay gates SDel (red) representing switching time. Quadratic blocks represent single- and two-qubit gates. (d) Impact of gate-execution ordering on overhead: (d1) target circuit, (d2) default ordering by qubit index, and (d3) distance-optimized ordering based on subsequent two-qubit gates.
• Figure 2: Overhead from time multiplexing single-qubit control for square-grid architectures (left column: 5$\times$5 grid; right column: 11$\times$11 grid). Each data point displayed is the median over 100 random circuit seeds; shaded areas show the interquartile range. (a, b) Serialization overhead as an increase in circuit duration compared to the routed circuit, as a function of the number of gates in random circuits. (c, d) The same serialization overhead as in (a, d), but now shown relative to the routed circuit duration, as a function of the number of gates in random circuits. (e, f) Breakdown of total circuit duration: translated circuit (black), qubit routing overhead (light blue), and serialization overhead for $k$ qubits per switch (blue, green, yellow), for random circuits with three different gate counts. The procedure for generating and compiling the circuits is detailed in Sec. \ref{['sec:time-multiplexing']}.
• Figure 3: Impact of time multiplexing on execution of quantum algorithms from the MQT Bench set for an 11$\times$11 grid. (a) Total circuit duration for serialized routed circuits (colored markers) and routed circuits without serialization (black crosses and dashed line) across different quantum algorithms, ordered by increasing gate count. (b) Relative overhead of serialization compared to the routed circuit duration (markers, left axis), with shaded areas indicating gate densities ($\rho_1$ pink, $\rho_2$ blue, $\rho_{\rm total}$ green; right axis) and different marker colors indicating different numbers of qubits per switch. The data points are medians over 20 transpiler seeds. The full names of the quantum algorithms are listed in Table \ref{['tab:fit_parameters']} in Appendix \ref{['app:modeling_scaling']}.
• Figure 4: Distribution of time multiplexing overhead across switch sizes on an 11$\times$11 grid, for the quantum algorithms from MQT Bench shown in Fig. \ref{['fig:line-mqt-grid121']}, using 20 different transpilation seeds. The histograms show the relative overhead (ratio of serialized to routed circuit duration) for different numbers of qubits per switch. The $+n$ notation to the right in the bottom histograms indicates $n$ additional counts beyond the histogram limits.
• Figure 5: Scaling of serialization overhead for random circuits on an 11$\times$11 square grid. For each gate count, 100 random circuits were generated. The number of single-qubit gates $N_1^\text{routed}$ is retrieved after routing, with slight variations due to optimizations and routing. The serialization overhead scales linearly with $N_1^\text{routed}$ and the single-qubit gate duration $t_\text{1q}$, but logarithmically with qubits per switch $k$. Predictions (solid lines) align well with the data without additional scaling factors.