TLGLock: A New Approach in Logic Locking Using Key-Driven Charge Recycling in Threshold Logic Gates

Abstract

Logic locking remains one of the most promising defenses against hardware piracy, yet current approaches often face challenges in scalability and design overhead. In this paper, we present TLGLock, a new design paradigm that leverages the structural expressiveness of Threshold Logic Gates (TLGs) and the energy efficiency of charge recycling to enforce key-dependent functionality at the gate level. By embedding the key into the gate's weighted logic and utilizing dynamic charge sharing, TLGLock provides a stateless and compact alternative to conventional locking techniques. We implement a complete synthesis-to-locking flow and evaluate it using ISCAS, ITC, and MCNC benchmarks. Results show that TLGLock achieves up to 30% area, 50% delay, and 20% power savings compared to latch-based locking schemes. In comparison with XOR and SFLL-HD methods, TLGLock offers up to 3x higher SAT attack resistance with significantly lower overhead. Furthermore, randomized key-weight experiments demonstrate that TLGLock can reach up to 100% output corruption under incorrect keys, enabling tunable security at minimal cost. These results position TLGLock as a scalable and resilient solution for secure hardware design.

Figures (5)

• Figure 1: A single Threshold Logic Gate (TLG) replacing a complex multi-level CMOS logic network.
• Figure 2: TLG architectures: Latch-type Low Power Threshold Logic (LCTL) and Charge Recycling Threshold Logic (CRTL).
• Figure 3: Proposed flow: [fill color=black, inner color=white, , inner xsep=0.5ex, inner ysep=0.5ex]1[fill color=black, inner color=white, , inner xsep=0.5ex, inner ysep=0.5ex]1 Threshold logic synthesis from a BLIF or BENCH file involving Boolean structure analysis and threshold cut computation. [fill color=black, inner color=white, , inner xsep=0.5ex, inner ysep=0.5ex]2[fill color=black, inner color=white, , inner xsep=0.5ex, inner ysep=0.5ex]2 TLGs with respective weights and thresholds post-synthesis. [fill color=black, inner color=white, , inner xsep=0.5ex, inner ysep=0.5ex]4[fill color=black, inner color=white, , inner xsep=0.5ex, inner ysep=0.5ex]4 Merging two TLGs via linear combination lee2016analytic. [fill color=black, inner color=white, , inner xsep=0.5ex, inner ysep=0.5ex]5[fill color=black, inner color=white, , inner xsep=0.5ex, inner ysep=0.5ex]5 Embedding key inputs with weights proportional to the input weight sum. [fill color=black, inner color=white, , inner xsep=0.5ex, inner ysep=0.5ex]6[fill color=black, inner color=white, , inner xsep=0.5ex, inner ysep=0.5ex]6 Extraction of weights and threshold values to be used in [fill color=black, inner color=white, , inner xsep=0.5ex, inner ysep=0.5ex]7[fill color=black, inner color=white, , inner xsep=0.5ex, inner ysep=0.5ex]7 for assigning them into their corresponding inputs. [fill color=black, inner color=white, , inner xsep=0.5ex, inner ysep=0.5ex]8[fill color=black, inner color=white, , inner xsep=0.5ex, inner ysep=0.5ex]8 TLG circuit synthesis and PnR (Place and Route) of the TLG circuits for performance extraction.
• Figure 4: Impact of key input weight assignment on power, delay, and corruption rate in a TLG. Balanced weights offer higher corruption but incur power/delay trade-offs.
• Figure 5: Normalized performance metrics a) Area, b) Power, and c) Delay overhead for latch-based (LCTL) and recycling-based (CRTL) architectures for c1355 across varying key configurations ($K = 10$ to $K = 25$).