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RF-Informed Graph Neural Networks for Accurate and Data-Efficient Circuit Performance Prediction

Anahita Asadi, Leonid Popryho, Inna Partin-Vaisband

TL;DR

This work presents a lightweight, data-efficient, and topology-aware graph neural network (GNN) framework for predicting key performance metrics of active RF circuit classes, such as low-noise amplifiers, mixers, voltage-controlled oscillators, and power amplifiers, using RFIC domain-informed feature indexing to enable cross-topology adaptability.

Abstract

Accurately predicting the performance of active radio frequency (RF) circuits is essential for modern wireless systems but remains challenging due to highly nonlinear, layout-sensitive behavior and the high computational cost of traditional simulation tools. Existing machine learning (ML) surrogates often require large datasets to generalize across various topologies or are not accurate on unseen circuits. This work presents a lightweight, data-efficient, and topology-aware graph neural network (GNN) framework for predicting key performance metrics of active RF circuit classes, such as low-noise amplifiers (LNAs), mixers, voltage-controlled oscillators (VCOs), and power amplifiers (PAs). The proposed framework employs RFIC domain-informed feature indexing to enable cross-topology adaptability by cheap encoding of functional device semantics (e.g., differential pair and varactor transistors) and efficient knowledge transfer. The surrogate model represents circuits using device-terminal graph abstractions to preserve fine-grained connectivity and transistor-level symmetry. The final model is generalized to a wide variety of classes by being trained in parallel. Experimental results demonstrate accurate modeling of multimodal and heavy-tailed RF performance distributions, achieving an average mean relative error (MRE) of 3.45%, an improvement of 9.2x compared to state-of-the-art. Furthermore, the method improves class-level generalization performance by ~161x compared to prior art, demonstrating its effectiveness for scalable and deployment-ready RF design automation.

RF-Informed Graph Neural Networks for Accurate and Data-Efficient Circuit Performance Prediction

TL;DR

This work presents a lightweight, data-efficient, and topology-aware graph neural network (GNN) framework for predicting key performance metrics of active RF circuit classes, such as low-noise amplifiers, mixers, voltage-controlled oscillators, and power amplifiers, using RFIC domain-informed feature indexing to enable cross-topology adaptability.

Abstract

Accurately predicting the performance of active radio frequency (RF) circuits is essential for modern wireless systems but remains challenging due to highly nonlinear, layout-sensitive behavior and the high computational cost of traditional simulation tools. Existing machine learning (ML) surrogates often require large datasets to generalize across various topologies or are not accurate on unseen circuits. This work presents a lightweight, data-efficient, and topology-aware graph neural network (GNN) framework for predicting key performance metrics of active RF circuit classes, such as low-noise amplifiers (LNAs), mixers, voltage-controlled oscillators (VCOs), and power amplifiers (PAs). The proposed framework employs RFIC domain-informed feature indexing to enable cross-topology adaptability by cheap encoding of functional device semantics (e.g., differential pair and varactor transistors) and efficient knowledge transfer. The surrogate model represents circuits using device-terminal graph abstractions to preserve fine-grained connectivity and transistor-level symmetry. The final model is generalized to a wide variety of classes by being trained in parallel. Experimental results demonstrate accurate modeling of multimodal and heavy-tailed RF performance distributions, achieving an average mean relative error (MRE) of 3.45%, an improvement of 9.2x compared to state-of-the-art. Furthermore, the method improves class-level generalization performance by ~161x compared to prior art, demonstrating its effectiveness for scalable and deployment-ready RF design automation.

Paper Structure

This paper contains 19 sections, 11 equations, 4 figures, 10 tables.

Table of Contents

  1. Introduction
  2. Related Work on GNNs
  3. Proposed Framework
  4. Graph Representation of RF Circuits
  5. GNN Architecture
  6. Experimental Setup
  7. Dataset Description
  8. Initialization
  9. Hyperparameters
  10. Loss Function
  11. Computational Cost
  12. Evaluation Metrics
  13. Experimental Results
  14. Topology-Specific Results
  15. Intra-Class Ablation Study
  16. ...and 4 more sections

Figures (4)

  • Figure 1: Proposed Circuit-to-Graph Conversion and Feature Extraction Method with Functionality-aware Feature Indexing.
  • Figure 2: Model Architecture: GENConv layers mimic KVL and KCL, while GraphNorm enables graph structure-awareness and numerical stability.
  • Figure 3: Parity plots, MRE, and sMAPE for a well-performing FoM, mixer PDC (blue shade), and two worse-performing FoMs, mixer CGain (orange shade) and VA VGain (green shade).
  • Figure 4: Comparison of per-circuit average inference latency for different RF circuits (LNA, Mixer, PA, VA, and VCO) with the model on CPU (0.57-4.37 milliseconds) and GPU (0.17-0.34 milliseconds) versus per-circuit average Spectre simulations runtime (6.73-11.69 seconds) and FALCON inference latency on GPU (0.63-2.22 milliseconds).