Fermion-to-Fermion Low-Density Parity-Check Codes

TL;DR

The paper addresses the resource overhead of simulating fermionic systems on qubit-based hardware by introducing fermion-to-fermion LDPC codes built from weakly-self-dual CSS codes and Majorana stabilizers, enabling multiple logical fermion modes with odd-weight Majorana operators. It develops two practical fermionic lattice-surgery methods to transfer and couple memory and processors while preserving code distance, and validates fault-tolerance via subsystem-code analysis and numerical experiments. Through extensive simulations, including code-capacity, phenomenological, and circuit-level noise with realistic decoders, the work demonstrates substantial error suppression and pseudo-thresholds above $0.1\%$ for several codes, and shows that the encoding rate can match qubit codes while maintaining low logical failure rates. Overall, this framework offers a scalable path to fault-tolerant, fermion-native quantum computation with potentially lower overhead for simulating fermionic dynamics.

Abstract

Simulating fermionic systems on qubit-based quantum computers often demands significant computational resources due to the requirement to map fermions to qubits. Thus, designing a fault-tolerant quantum computer that operates directly with fermions offers an effective solution to this challenge. Here, we introduce a protocol for fault-tolerant fermionic quantum computation utilizing fermion-to-fermion low-density parity-check (LDPC) codes. Our method employs a fermionic LDPC memory, which transfers its state to fermionic color code processors, where logical operations are subsequently performed. We propose using odd-weight logical Majorana operators to form the code space, serving as memory for the fermionic LDPC code, and provide an algorithm to identify these logical operators. We present examples showing that the encoding rate of fermionic codes often matches that of qubit codes, while the logical failure rate can be significantly lower than the physical error rate. Furthermore, we propose two methods for performing fermionic lattice surgery to facilitate state transfer. Finally, we simulate the dynamics of a fermionic system using our protocol, illustrating effective error suppression.

Figures (18)

• Figure 1: Schematic illustration of fault-tolerant fermionic quantum computation framework. The architecture comprises three components: fermionic memory implemented using fermionic LDPC codes, fermionic processor implemented using fermionic color codes to execute logical operations, and fermionic interface composed of ancilla fermions serving as a critical bridge for communication between memory and processor.
• Figure 2: (a) Illustration of the circuit-level noise model where the syndrome extraction transfer circuits used to establish entanglement between data fermions and ancilla qubits are noisy. The initial states are physical $|0\rangle$ states for fermions. In the end, a transversal measurement on all physical fermion modes in the particle number basis is performed. Logical failure rate $p_L$ versus physical error rate $p$ under (b) phenomenological and (c) circuit-level noise model for fermionic $[[20,4,4]]_{\text{f}}$, $[[36,4,6]]_{\text{f}}$ and $[[44,4,7]]_{\text{f}}$ double-chain bicycle codes. We also perform a power law fit to the data according to the fitting formula $p_L\sim p^\alpha$ with $\alpha=2.21, 3.06, 4.3$ in (b) and $\alpha=2.12, 3.46, 4.54$ in (c), and the gray lines represent the probability that at least an error occurs on four physical fermion modes. Here, the Tesseract decoder beni2025tesseractdecoder is employed, and the results obtained using the belief propagation and ordered-statistical decoding (BP+OSD) liang2025lowroffe_decoding_2020 algorithm are presented in Supplemental Material.
• Figure 3: (a) Quantum circuit to transfer a logical fermionic state $|\overline{\psi}\rangle_A$ to code block $B$ (initialized as $|\overline{0}\rangle_B$). The protocol involves: (i) measuring $\text{i}\overline{\gamma}_A\overline{\gamma}_B$ and applying the $Z$ gate of $\exp(\text{i}\pi\overline{n}_B)$, provided the measurement result is $-1$; (ii) measuring the logical particle number $\overline{n}_A$ and applying two braiding gates and one fermionic $Z$ gate, if the measurement outcome is $1$; (iii) applying a phase rotation $S$ gate to the state in the processor. The validation of this circuit is provided in Supplemental Material. (b) Illustration of the first method for lattice surgery achieving fault-tolerant measurements of $\text{i}\overline{\gamma}_A \overline{\gamma}_B$ in the case with $|\overline{\gamma}_A|=|\overline{\gamma}_B|$. In this example, code $B$ is a $d=5$ fermionic color code, and code $A$ is a fermionic LDPC code containing five Majorana operators in the support of $\overline{\gamma}_A$. The empty circles represent the $\gamma$-type Majorana operators in blocks $A$ and $B$. Several pairs of ancilla Majorana operators are introduced with each horizontal pair represented by yellow and gray circles to denote $\gamma$-type and $\gamma^\prime$-type Majorana operator forming a complex fermion. The $\gamma$-type stabilizer generators at the boundary, connected to ancilla fermions, are modified to incorporate the ancilla Majorana operators (green rhombuses). Measurement and gauge stabilizer generators are depicted as blue squares and red triangles, respectively. The product of these stabilizer generators yields the joint logical operator $\text{i}\overline{\gamma}_A \overline{\gamma}_B$. The $\gamma^\prime$-type Majorana stabilizers remain unchanged.
• Figure 4: (a) Quantum circuit used to benchmark our protocol. We first initialize the system in the logical state $\left|\overline{0}\overline{1}\overline{0}\overline{1}\right\rangle$ and then apply three tunneling gates with each gate executing the operation ${T}_{j,j+1}= \exp(\text{i} \pi (\overline{c}_j^\dagger \overline{c}_{j+1} + \text{H.c.})/2)$. Onsite measurements of $\overline{n}_j=\overline{c}_j^\dagger \overline{c}_j$ with $j=0,1,2$ are then performed, followed by a fermionic swap (fSWAP) gate if the measurement result is zero. The unitary gates and feedback process constitute a module, which is executed consecutively multiple times. (b) The expectation value of logical particle numbers at site $1$ and $4$ with respect to time which is characterized by the number of executed modules. We see that the simulation under circuit-level noise with error correction (filled blue circles and squares) is close to the noiseless simulation result (the dotted-dashed lines), in stark contrast to the simulation results under noise without error correction (filled red circles and squares). In the simulation, we apply the first method for lattice surgery. Results using the second method are provided in the Supplemental Material. Here, we set the physical error rate $p=10^{-4}$. The error bars are hidden behind the symbols.
• Figure 5: Illustration of modified stabilizers in (a), measurement stabilizers in (b), and gauges stabilizers in (c) for a specific case of fermionic lattice surgery using method 1. Before merging, the original stabilizers include those of the fermionic LDPC code, the color code, and the stabilizers of ancilla Majorana operators (each stabilizer includes a pair of ancilla Majorana operators forming a complex fermion).

Theorems & Definitions (2)

• Theorem 1.1
• proof