ListenToJESD204B: A Lightweight Open-Source JESD204B IP Core for FPGA-Based Ultrasound Acquisition systems

TL;DR

ListenToJESD204B delivers a compact, open-source JESD204B Subclass 1 receiver targeted at FPGA-based ultrasound front-ends. The SystemVerilog IP supports up to four lanes at $12.8\,\mathrm{Gbps}$ with deterministic latency and achieves a roughly $79\%$ reduction in LUT/FF utilization versus a leading commercial implementation, validated through simulation and hardware using TI AFE58JD48 to acquire $80\,\mathrm{MSPS}$, $16$-bit data over two high-speed links for extended operation. The architecture features per-lane elastic buffering, SYSREF-synchronized LMFC, and optional LFSR descrambling, enabling scalable, open, reproducible, high-channel-count ultrasound systems and real-time processing pipelines. The work enables open hardware proliferation in biomedical ultrasound by reducing cost and complexity while maintaining protocol compliance and timing determinism, with clear paths for extensions to Subclass-0/2 and transmitter support.

Abstract

The demand for hundreds of tightly synchronized channels operating at tens of MSPS in ultrasound systems exceeds conventional low-voltage differential signaling links' bandwidth, pin count, and latency. Although the JESD204B serial interface mitigates these limitations, commercial FPGA IP cores are proprietary, costly, and resource-intensive. We present ListenToJESD204B, an open-source receiver IP core released under a permissive Solderpad 0.51 license for AMD Xilinx Zynq UltraScale+ devices. Written in synthesizable SystemVerilog, the core supports four GTH/GTY lanes at 12.8 Gb/s and provides cycle-accurate AXI-Stream data alongside deterministic Subclass~1 latency. It occupies only 107 configurable logic blocks (approximately 437 LUTs), representing a 79\% reduction compared to comparable commercially available IP. A modular data path featuring per-lane elastic buffers, SYSREF-locked LMFC generation, and optional LFSR descrambling facilitates scaling to high lane counts. We verified protocol compliance through simulation against the Xilinx JESD204C IP in JESD204B mode and on hardware using TI AFE58JD48 ADCs. Block stability was verified by streaming 80 MSPS, 16-bit samples over two 12.8 Gb/s links for 30 minutes with no errors.

Figures (6)

• Figure 1: Block diagram of a 256-channel open-ultrasound front-end. The ListenToJESD204B core converts 32 JESD204B lanes to parallel data, which is then losslessly compressed and stored, as well as reconstructed for real-time imaging.
• Figure 2: High-Level Architecture of the JESD204B Receiver
• Figure 3: Simulation-based verification setup for the JESD204B receiver IP core. The testbench uses a golden output to evaluate the functional correctness of the implemented design
• Figure 4: Acquisition and reconstruction of a 5MHz sine wave using the JESD204 RX IP
• Figure 5: Acquisition of scatterers on CIRS 040GSE Ultrasound Phantom