MAHL: Multi-Agent LLM-Guided Hierarchical Chiplet Design with Adaptive Debugging

TL;DR

MAHL introduces a six-agent, hierarchical LLM-guided framework for 2.5D chiplet design to automate AI-to-hardware mapping and design space exploration. By combining hierarchical prompts, retrieval-augmented HDL generation, a Diverseflow Validator, and a multi-granularity design space explorer with a layout configurator, MAHL addresses flattened code, validation cost, and parameter optimization challenges. Empirical results show significant gains in generation accuracy (e.g., Pass@1/Pass@5) and competitive PPA relative to expert-based baselines across simple RTL designs and chiplet IPs for models like BERT, GPT, and LLaMA. The framework demonstrates the potential to accelerate automatic chiplet design and produce hardware tuned to specific AI workloads with practical hardware performance comparable to human-designed baselines.

Abstract

As program workloads (e.g., AI) increase in size and algorithmic complexity, the primary challenge lies in their high dimensionality, encompassing computing cores, array sizes, and memory hierarchies. To overcome these obstacles, innovative approaches are required. Agile chip design has already benefited from machine learning integration at various stages, including logic synthesis, placement, and routing. With Large Language Models (LLMs) recently demonstrating impressive proficiency in Hardware Description Language (HDL) generation, it is promising to extend their abilities to 2.5D integration, an advanced technique that saves area overhead and development costs. However, LLM-driven chiplet design faces challenges such as flatten design, high validation cost and imprecise parameter optimization, which limit its chiplet design capability. To address this, we propose MAHL, a hierarchical LLM-based chiplet design generation framework that features six agents which collaboratively enable AI algorithm-hardware mapping, including hierarchical description generation, retrieval-augmented code generation, diverseflow-based validation, and multi-granularity design space exploration. These components together enhance the efficient generation of chiplet design with optimized Power, Performance and Area (PPA). Experiments show that MAHL not only significantly improves the generation accuracy of simple RTL design, but also increases the generation accuracy of real-world chiplet design, evaluated by Pass@5, from 0 to 0.72 compared to conventional LLMs under the best-case scenario. Compared to state-of-the-art CLARIE (expert-based), MAHL achieves comparable or even superior PPA results under certain optimization objectives.

Figures (6)

• Figure 1: The overview of the MAHL framework. MAHL framework consists of 6 agents, including an AI-Hardware Hierarchical Parser, a Hierarchical Description Generator, a Retrieval-Augmented Code Generator, an Adaptive Validator, a Multi-granularity Design Space Explorer and a Configurator.
• Figure 2: Hierarchical description generation flow incorporates (1) AI-Hardware Hierarchical Parser and (2) Hierarchical Module Description Generator.
• Figure 3: RTL implementation and validation flow, including (1) Retrieval-Augmented Code Generator and (2) Diverseflow Validator.
• Figure 4: Workflow of Multi-Granularity Design Space Explorer.
• Figure 5: Layout of one chiplet design for BERT algorithm.