BioGAP-Ultra: A Modular Edge-AI Platform for Wearable Multimodal Biosignal Acquisition and Processing

TL;DR

BioGAP-Ultra presents a modular, open-source wearable platform built around the GAP9 edge-AI SoC to enable synchronized multimodal biosignal acquisition (EEG/EMG/ECG/PPG) with on-device processing. It delivers expandable hardware, higher channel counts, and real-time edge inference across three wearable form factors (headband, sleeve, chestband) with demonstrated tasks including SSVE P-based EEG, EMG gesture-phase classification, and PAT estimation. The work shows favorable power and throughput characteristics, enabling long battery life and privacy-preserving onboard computation, while providing a complete hardware-software stack for researchers. It also discusses future directions toward additional modalities and foundation-model deployment on wearables, highlighting broad applicability in HMI, healthcare monitoring, and neuro/muscular research.”

Abstract

The growing demand for continuous physiological monitoring and human-machine interaction in real-world settings calls for wearable platforms that are flexible, low-power, and capable of on-device intelligence. This work presents BioGAP-Ultra, an advanced multimodal biosensing platform that supports synchronized acquisition of diverse electrophysiological and hemodynamic signals such as EEG, EMG, ECG, and PPG while enabling embedded AI processing at state-of-the-art energy efficiency. BioGAP-Ultra is a major extension of our previous BioGAP design aimed at meeting the rapidly growing requirements of wearable biosensing applications. It features (i) increased on-device storage (x2 SRAM, x4 FLASH), (ii) improved wireless connectivity (supporting up to 1.4 Mbit/s bandwidth, x4 higher than BioGAP), (iii) enhanced number of signal modalities (from 3 to 5) and analog input channels (x2). Further, it is accompanied by a real-time visualization and analysis software suite that supports the hardware design, providing access to raw data and real-time configurability on a mobile phone. Finally, we demonstrate the system's versatility through integration into various wearable form factors: an EEG-PPG headband consuming 32.8 mW, an EMG sleeve at 26.7 mW, and an ECG-PPG chestband requiring only 9.3 mW for continuous acquisition and streaming, tailored for diverse biosignal applications. To showcase its edge-AI capabilities, we further deploy two representative on-device applications: (1) ECG-PPG-based PAT estimation at 8.6 mW, and (2) EMG-ACC-based classification of reach-and-grasp motion phases, achieving 79.9 % $\pm$ 5.7 % accuracy at 23.6 mW. All hardware and software design files are also released open-source with a permissive license.

Figures (15)

• Figure 1: Overview of the proposed system and integration in multiple form factors. Top left: sketch of a person wearing the devices. (A) headband: the BioGAP-Ultra platform is integrated in a textile headband with 16 SoftPulse dry EEG active electrodes, which can be coupled to a compact PPG sensing board on the earlobe; (B) chestband: the BioGAP-Ultra platform is integrated in a chestband with flat, dry electrodes for ECG measurements; (C) arm sleeve: BioGAP-Ultra uses the EMG sensing board and is integrated in a sleeve with flat and fully-dry EMG channels over the forearm (12 channels) and upper arm (4 channels).
• Figure 2: Normalized radar chart quantitatively comparing BioGAP-Ultra (this work) to BioGAP v1 frey_2023_BioGAP and to existing SoA platforms across five main metrics (throughput, channel count, number of modalities, onboard memory, and onboard computing efficiency). Considering the total area covered, BioGAP-Ultra outperforms all SoA systems.
• Figure 3: Photo of the Mainboard. The board comprises a breakaway section with pin headers and buttons to facilitate programming and debugging.
• Figure 4: Block diagram of the Mainboard, with description of the interfaces. Power supply connections are not shown.
• Figure 5: Block diagram of the Mainboard power management. The upper TPS22916 load switches are controlled by nRF5340 GPIOs, the lower ones by GAP9. V$_{SYS}$, V$_{D1}$, V$_{D2}$, V$_{D3}$, V$_{A1}$ and V$_{A2}$ are all controllable and programmable through a common I2C bus by both SoCs.