Image2Net: Datasets, Benchmark and Hybrid Framework to Convert Analog Circuit Diagrams into Netlists

TL;DR

This paper addresses the data gap hindering LLM-assisted analog IC design by converting image-based circuit diagrams into textual netlists. It introduces Image2Net, a hybrid CV/ML framework, and releases diverse datasets plus a Netlist Edit Distance (NED) metric for robust evaluation. The benchmark shows 80.77% netlist-success rate with a mean NED of 0.659, and ablation studies indicate strong gains from specialized jumper handling (NED ~0.116) over prior methods. Together, the open-source datasets and GED-based evaluation provide a practical path to improving LLM-driven analog circuit design.

Abstract

Large Language Model (LLM) exhibits great potential in designing of analog integrated circuits (IC) because of its excellence in abstraction and generalization for knowledge. However, further development of LLM-based analog ICs heavily relies on textual description of analog ICs, while existing analog ICs are mostly illustrated in image-based circuit diagrams rather than text-based netlists. Converting circuit diagrams to netlists help LLMs to enrich the knowledge of analog IC. Nevertheless, previously proposed conversion frameworks face challenges in further application because of limited support of image styles and circuit elements. Up to now, it still remains a challenging task to effectively convert complex circuit diagrams into netlists. To this end, this paper constructs and opensources a new dataset with rich styles of circuit diagrams as well as balanced distribution of simple and complex analog ICs. And a hybrid framework, named Image2Net, is proposed for practical conversion from circuit diagrams to netlists. The netlist edit distance (NED) is also introduced to precisely assess the difference between the converted netlists and ground truth. Based on our benchmark, Image2Net achieves 80.77% successful rate, which is 34.62%-45.19% higher than previous works. Specifically, the proposed work shows 0.116 averaged NED, which is 62.1%-69.6% lower than state-of-the-arts. Our datasets and benchmark are available at https://github.com/LAD021/ci2n_datasets.

Figures (11)

• Figure 2: A circuit diagram image and its corresponding graph. The schematic diagram in Fig.(a) encompasses 3 NMOSs, 2 PMOSs, 1 Resistor, and 4 NETs. In Fig.(b), there are altogether 3 types of nodes, namely PMOS, NMOS, NET. There are 4 types of edges, namely PMOS_Gate, PMOS_D_S, NMOS_Gate, NMOS_D_S
• Figure 3: Device identification Examples.
• Figure 4: Wire detection algorithm. Fig.(a) is the raw image. Fig.(b) represents the result of the skeleton algorithm. Fig.(c) represents the result of the removing of texts. Fig.(d) shows the final wire detection result.
• Figure 5: How to pair the ports of a jumper. For a jumper, we name the ports in clockwise order and treat ports in opposite directions as pairs, and the paired ports and their associated nets are connected. For a connection that is not a jumper, all nets connected to it are connected to each other.
• Figure 6: Post processing. Following the working flow, the first figure is the raw image of the circuit diagram. the second figure is the result of connection detection before post processing. In the next steps, the same color means the wires related are all connected. the third to fifth figures shows the merge procedures for cross ports, jumpers, and gnd.