Theoretical Investigation of Performance-Improved Ferroelectric Tunnel Junction Based on Trap-Assisted Tunneling

TL;DR

The paper addresses the low on-state current density and limited on-off current ratio in CMOS-compatible HfO$_2$-based ferroelectric tunnel junctions by proposing trap-assisted tunneling (TAT) as the dominant conduction mechanism. It develops a self-consistent, multi-mechanism FTJ model that couples ferroelectric switching with direct tunneling, Fowler–Nordheim tunneling, and TAT, incorporating phonon-assisted trap dynamics and trap occupancy. Systematic analysis shows that trap energy levels, trap density, and interfacial band offsets critically govern $J_{ m ON}$ and TER, enabling optimized trap configurations that maximize $J_{ m ON}$ while preserving a large $J_{ m ON}/J_{ m OFF}$. Through device-structure optimization, including thickness scaling and tuning the TIL/FE ratio, the study demonstrates $J_{ m ON} > 10^{5}$ A/cm$^2$ and $J_{ m ON}/J_{ m OFF} > 170$ at low write/read voltages, outperforming conventional FTJs. These findings provide design guidelines for high-performance ferroelectric memory in nanoscale IMC applications and suggest a path toward practical, low-power, high-density non-volatile memory solutions.

Abstract

CMOS-compatible HfO2-based ferroelectric tunnel junction (FTJ) has attracted significant attention as a promising candidate for in-memory computing (IMC) due to its extremely low power consumption. However, conventional FTJs face inherent challenges that hinder their practical applications. Insufficient current density and limited on-off current ratios in FTJs are primarily constrained by their dependence on direct and Fowler-Nordheim tunneling mechanisms. Building on previous experimental results, this paper proposes a trap-assisted tunneling (TAT)-based FTJ that leverages the TAT mechanism to overcome these limitations. A comprehensive FTJ model integrating ferroelectric switching, direct, Fowler-Nordheim tunneling, and TAT mechanisms is developed, enabling detailed analyses of the trap conditions and their impact on performance. Through systematic optimization of trap parameters and device structure, the simulated TAT-based FTJ achieves ultra-high current density and a remarkable on-off current ratio, meeting the nanoscale IMC requirements. The results highlight the potential of TAT-based FTJs as high-performance memory solutions for IMC applications.

Figures (4)

• Figure 1: (a) Comparative schematic of conventional and TAT-based FTJ mechanisms. Conventional FTJ suffers from low $J_{\mathrm{ON}}$ and low $J_{\mathrm{ON}}/J_{\mathrm{OFF}}$ ratio, whereas TAT-based FTJ achieves high $J_{\mathrm{ON}}$ and high $J_{\mathrm{ON}}/J_{\mathrm{OFF}}$ ratio through appropriate trap modulation. (b) Reproduced experimental and (c) simulated J-V curves w/ and w/o 1.5 nm Al$_{2}$O$_{3}$ in 3 nm HZO FTJ, with sweep voltage $\pm1\;\mathrm{V}$. (d) The schematic of the device structure and trap conditions of the simulated FTJ.
• Figure 2: (a) $E_{\mathrm{T}}$ dependence of $J_{\mathrm{TAT}}$ under $V_{\mathrm{write}}=1\;\mathrm{V}$ and $V_{\mathrm{read}}=0.1\;\mathrm{V}$. (b) Schematic illustration of the single $E_{\mathrm{T}}$ dependence of $J_{\mathrm{TAT}}$ under positive $V_{\mathrm{read}}$, with $E_{\mathrm{TE}}$ and $E_{\mathrm{BE}}$ being the Fermi level of TE and BE. (c) Single $E_{\mathrm{T}}$ dependence of $J_{\mathrm{TAT}}$ under $V_{\mathrm{write}}=1\;\mathrm{V}$ and $V_{\mathrm{read}}=0.1\;\mathrm{V}$.
• Figure 3: $N_{\mathrm{T}}$ dependencies of (a) $\mathrm{J}_{\mathrm{TAT}}$ and (b) CNL under $V_{\mathrm{write}}=1\;\mathrm{V}$ and $V_{\mathrm{read}}=0.1\;\mathrm{V}$, with $\mathrm{E}_{\mathrm{BE}}$ set as the zero-energy reference. (c) J-V curves of the 1.5-nm Al$_{2}$O$_{3}$/3-nm HZO/0.6-nm BIL TAT-based FTJ after trap condition optimization and its conventional counterpart under sweep voltage $\pm1\;\mathrm{V}$.
• Figure 4: (a) Thickness scaling of TAT-based FTJ and (b) thickness proportion modulation of TAT-based FTJ and conventional FTJ under $V_{\mathrm{write}}=1\;\mathrm{V}$ and $V_{\mathrm{read}}=0.1\;\mathrm{V}$. (c) J-V curves of the 0.35-nm Al$_{2}$O$_{3}$/2.15-nm HZO/0.6-nm BIL TAT-based FTJ and the 2.5-nm HZO/0.6-nm BIL conventional FTJ after device structure optimization under sweep voltage $\pm1\;\mathrm{V}$.