IzhiRISC-V -- a RISC-V-based Processor with Custom ISA Extension for Spiking Neuron Networks Processing with Izhikevich Neurons

TL;DR

This work tackles the energy-inefficiency of spiking neural networks on general-purpose hardware by introducing IzhiRISC-V, a RISC-V ASIP augmented with a neuromorphic NPU and a DCU to support single-cycle Izhikevich neuron updates and AMPA-like decay. The proposed ISA extension uses four instructions (two configuration, two processing) with fixed-point formats, enabling efficient neuron state updates within a standard RISC-V pipeline. Hardware implementation and validation on an FPGA, along with standard-cell mapping for 45 nm and 7 nm libraries, demonstrate practical performance and scalability potential, including a 1.64x speedup for a 1000-neuron network and a 40x speedup for Sudoku CSP solving, highlighting the approach’s viability for large-scale neuromorphic systems. The results indicate that integrating dedicated neuromorphic units into a conventional processor can yield high throughput and energy-efficient SNN processing, paving the way for HPC-grade IzhiRISC-V clusters and NoC-enabled multi-core deployments.

Abstract

Spiking Neural Network processing promises to provide high energy efficiency due to the sparsity of the spiking events. However, when realized on general-purpose hardware -- such as a RISC-V processor -- this promise can be undermined and overshadowed by the inefficient code, stemming from repeated usage of basic instructions for updating all the neurons in the network. One of the possible solutions to this issue is the introduction of a custom ISA extension with neuromorphic instructions for spiking neuron updating, and realizing those instructions in bespoke hardware expansion to the existing ALU. In this paper, we present the first step towards realizing a large-scale system based on the RISC-V-compliant processor called IzhiRISC-V, supporting the custom neuromorphic ISA extension.

Figures (5)

• Figure 1: Overall architecture of the IzhiRISC-V core, with added NPU and DCU marked in green.
• Figure 2: Raster plot of the 80-20 IZH network simulation.
• Figure 3: Comparison of ISI histograms for different implementations of 80-20 network (top row - MATLAB (left - double precision, right - fixed-point), bottom row - IzhiRISC-V.
• Figure 4: Graph showing the inhibitory connections from an example spiking neuron (green) to other neurons in the "multi-level" WTA network in Sudoku solver (denoted in blue). The dashed lines around the 3x3 grid relate to the 3x3 subgrid of the 9x9 Sudoku board. The indices [x,y,z] indicate the row and column of a particular cell within the 9x9 Sudoku board, and the last index indicates which digit (1-9) the neuron is supposed to represent. The small subnetwork on the bottom right relates to the digits 1-9.
• Figure 5: Final floorplan of an IzhiRISC-V core on both the FreePDK 45 nm (left) and ASAP 7 nm (right) process, showing the NPU and DCU in comparison to other blocks in the pipeline.