It's not a FAD: first results in using Flows for unsupervised Anomaly Detection at 40 MHz at the Large Hadron Collider
Francesco Vaselli, Chang Sun, Thea Aarrestad, Dimitrios Danopoulos, Roope Oskari Niemi, Maciej Mikolaj Glowacki, Katya Govorkova, Vladimir Loncar, Felice Pantaleo, Maurizio Pierini
TL;DR
This work tackles real-time unsupervised anomaly detection at the LHC Level-1 trigger by deploying a Continuous Normalizing Flow (CNF) trained with Flow Matching. It introduces a hardware-friendly anomaly score, AS(x) = ||v_t(x, t | φ)||^2, enabling a single-pass FPGA inference suitable for 40 MHz operation and FPGA resource constraints. The approach demonstrates competitive anomaly detection performance against a VAE baseline while enabling aggressive quantization (PTQ and HGQ) that reduces latency to as low as tens of nanoseconds and uses a small FPGA footprint. These results establish CNFs as a viable model-agnostic tool for real-time discovery in high-rate collider environments and outline clear avenues for further optimization and score diversification.
Abstract
We present the first implementation of a Continuous Normalizing Flow (CNF) model for unsupervised anomaly detection within the realistic, high-rate environment of the Large Hadron Collider's L1 trigger systems. While CNFs typically define an anomaly score via a probabilistic likelihood, calculating this score requires solving an Ordinary Differential Equation, a procedure too complex for FPGA deployment. To overcome this, we propose a novel, hardware-friendly anomaly score defined as the squared norm of the model's vector field output. This score is based on the intuition that anomalous events require a larger transformation by the flow. Our model, trained via Flow Matching on Standard Model data, is synthesized for an FPGA using the hls4ml and da4ml libraries. We demonstrate that our approach effectively identifies a variety of beyond-the-Standard-Model signatures with performance comparable to existing machine learning-based triggers. The algorithm achieves a latency of a few hundred nanoseconds, or even less when using advanced quantization techniques, and requires minimal FPGA resources, establishing CNFs as a viable new tool for real-time, data-driven discovery at 40 MHz.
