Virtual Sensing for Solder Layer Degradation and Temperature Monitoring in IGBT Modules

Abstract

Monitoring the degradation state of Insulated Gate Bipolar Transistor (IGBT) modules is essential for ensuring the reliability and longevity of power electronic systems, especially in safety-critical and high-performance applications. However, direct measurement of key degradation indicators - such as junction temperature, solder fatigue or delamination - remains challenging due to the physical inaccessibility of internal components and the harsh environment. In this context, machine learning-based virtual sensing offers a promising alternative by bridging the gap from feasible sensor placement to the relevant but inaccessible locations. This paper explores the feasibility of estimating the degradation state of solder layers, and the corresponding full temperature maps based on a limited number of physical sensors. Based on synthetic data of a specific degradation mode, we obtain a high accuracy in the estimation of the degraded solder area (1.17% mean absolute error), and are able to reproduce the surface temperature of the IGBT with a maximum relative error of 4.56% (corresponding to an average relative error of 0.37%).

Figures (8)

• Figure 1: Idealized geometries used in this study: (a) Overview of the system with the diode on the left and the chip on the right. (b) Delamination scenario: View from top onto the chip solder layer (other components of the system are hidden) at different degradation states. The different states are shown on top of each other. (c) Solder voiding scenario: Exemplary void configuration at a lost solder layer fraction of $\alpha=25.6\%$ (view from top onto the chip solder layer).
• Figure 2: Architecture of the edge-conditioned graph attention network for chip surface temperature prediction. An example of a graph extracted from the dataset, highlighting the temperature distribution (in Kelvin) across chip surface nodes, is shown on the right as the output of the predictive model.
• Figure 3: Predicted and true solder area fraction per chip in the delamination test dataset for increasing levels of synthetic $T_\mathrm{j}$ noise maignitude ($\gamma$).
• Figure 4: Difference in mean absolute error per chip zone between the standard graph network model and the physics-regularized variant with the heat equation constraint, in the delamination test dataset. Errors are aggregated over a $25 \times 25$ spatial grid.
• Figure 5: Absolute prediction errors for maximum chip temperature across the test set, comparing the standard graph network model and the physics-regularized variant with the heat equation constraint.