Logical accreditation: a framework for efficient certification of fault-tolerant computations

TL;DR

This paper addresses the challenge of certifying fault-tolerant quantum computations performed on encoded logical qubits by introducing logical accreditation, a scalable, device-independent framework. It combines target and trap logical circuits with a randomised compiling scheme that twirls noise into logical stochastic Pauli channels, enabling a provable TVD bound between experimental and ideal outputs derived from trap data. The framework supports robustness to broad noise models, provides complete and sound certification guarantees, and includes a novel method to twirl non-transversal non-Clifford gates beyond the T gate. Through numerical simulations of IQP and Trotterised Hamiltonian circuits, the authors demonstrate the crossover where encoded computations outperform unencoded ones and outline practical applications such as extending entropy-density benchmarking and evaluating quantum error mitigation for logical circuits, offering a path toward scalable, certifiable fault-tolerant quantum computation.

Abstract

As fault-tolerant quantum computers scale, certifying the accuracy of computations performed with encoded logical qubits will soon become classically intractable. This creates a critical need for scalable, device-independent certification methods. In this work, we introduce logical accreditation, a framework for efficiently certifying quantum computations performed on logical qubits. Our protocol is robust against general noise models, far beyond those typically considered in performance analyses of quantum error-correcting codes. Through numerical simulations, we demonstrate that logical accreditation can scalably certify quantum advantage experiments and indicate the crossover point where encoded computations begin to outperform physical computations. The framework also enables evaluation of whether logical error rates are sufficiently low that error mitigation can be efficiently performed, extends entropy benchmarking to the regime of fault-tolerant computation, and upper-bounds the infidelity of the logical output state of a computation. Underlying the framework is a novel randomised compilation scheme that converts arbitrary logical circuit noise into stochastic Pauli noise. This scheme includes a method for twirling non-transversal logical gates beyond the standard T-gate, resolving an open problem posed by [Piveteau et al. PRL 127, 200505 (2021)]. By bridging fault-tolerant computation and computational certification, logical accreditation offers a scalable, practical means of certifying the accuracy of quantum computations performed using encoded logical qubits.

Figures (20)

• Figure 1: (a) The fault-tolerant quantum computing stack with the logical accreditation layer positioned between the logical control and the quantum algorithm layers. (b) Logical accreditation is performed with a quantum device and a classical processing unit (CPU). The input is a classical description of the target computation. This is used to compile both the target and trap circuits according to the required circuit structure and gate set. These circuits are run on the quantum device in a randomised order, and the measured bit strings are recorded on the CPU. The trap circuit outputs are then post-processed on the CPU to certify the target circuit output. To obtain $N$ certified samples, the sampling procedure is repeated $N$ times. The output is a certified set of $N$ bit string samples from the target circuit.
• Figure 2: Numerical simulation results of logical accreditation applied to IQP and Trotterised circuits. Circuits were run in three regimes: (i) noisy physical qubits (labelled NISQ), (ii) logical qubits without magic state purification (labelled PFTQC), and (iii) logical qubits with magic state purification (labelled FTQC). Logical error rates were modelled using surface code parameters with code distance $d=11$. Each protocol run used $500$ trap circuits. The method from ferracin_experimental_2021 was applied to obtain the TVD bounds for NISQ circuits, while for PFTQC and FTQC circuits logical accreditation was instead used. In (a) and (b), TVD upper-bounds are plotted against physical error rate for IQP and Trotterised circuits respectively; the number of circuit gate layers was fixed at 40. In (c) and (d), TVD upper-bounds are plotted against the number of circuit gate layers again for each circuit type; the physical error rate was fixed at $p_{\text{phys}} = 10^{-3}$.
• Figure 3: The logical circuit structure used for compilation of target and trap circuits, including state preparation and measurement. The logical gate layers are numbered by subscript with their ordering in time. The bracketed parts of the circuits indicate a repeated structure, with $m \in \{1,\ldots,D\}$, where the gates within each of the layers can change between repetitions. The circuit diagram in (a) shows the structure used to compile the target circuit, where the notation $\mathcal{S}$ denotes a layer of single-qubit Clifford gates, and $\mathcal{G}$ a gate layer that can contain multi-qubit Clifford gates, non-Clifford gates and identity gates. The circuit diagram in (b) shows the trap circuit structure used for compilation, where $\mathcal{H}$ denotes a layer of Hadamard gates, with $t \in \{0,1\}$, $\mathcal{W}$ a single-qubit randomising gate layer containing $S$, $S^{\dagger}$ and $H$ gates, and $\mathcal{J}$ a gate layer that can contain multi-qubit Clifford gates, trap circuit versions of the corresponding non-Clifford gates found in the target circuit, and identity gates. The logical randomised compiling gate layers are omitted from these circuit diagrams for the sake of simplicity.
• Figure 4: Soundness heatmap for IQP circuit sampling. This heatmap shows the trap circuit false positive rates for different numbers of logical qubits and physical error rates for IQP circuit sampling in the regime of full fault-tolerance (FTQC). A logical depolarising noise model was used for the numerical simulations, and the false positive events resulted from error stabilisation and cancellation effects. The false positive rates observed are well below the analytical soundness bounds provided in Section \ref{['sec:comp_and_sound']}
• Figure 5: Region of possible quantum advantage for IQP circuit sampling depending on $T$ gate noise and number of $T$ gates. The solid line on the plot is the maximum number of noisy $T$ gates such that the quantum advantage threshold derived in bremner_average-case_2016 is satisfied, plotted as a function of the $T$ gate error rate. It is assumed that Clifford gates are error-free, and circuit noise originates solely from $T$ gates. The best-known classical algorithms can simulate quantum circuits with up to roughly 50 $T$ gates bravyi_improved_2016pashayan_fast_2022. This threshold number of $T$ gates is included as the dashed horizontal line on the plot. The shaded region between the dashed and solid lines indicates the parameter regime where a quantum advantage is possible.

Theorems & Definitions (16)

• Theorem 1
• Theorem 2
• Lemma 3
• Lemma 4
• Lemma 5
• Lemma 6
• proof
• proof
• Lemma 7
• proof