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Analog Solver Circuit for Linear Symmetric Positive-Definite Systems at a Complexity Independent of Matrix Size

Osama Abdelaleim, Arun Prakash, Ayhan Irfanoglu, Veljko Milutinovic

TL;DR

The paper introduces a novel analog compute-in-memory solver that directly maps SPD linear systems $Ax=b$ to a resistive network, achieving unprecedented speed by transforming to a $2n\times2n$ formulation that minimizes active (negative) components. For symmetric diagonally dominant (SDD) matrices the network becomes purely passive, yielding $O(1)$-time convergence, while for general SPD matrices the convergence is independent of problem size and governed by spectral properties such as the smallest eigenvalue and diagonal dominance deviation. The design uses a cross-point memristor array and a carefully chosen diagonal matrix $D$ to ensure positive definiteness and efficient hardware mapping, with extensive SPICE and Monte Carlo-style robustness analyses under device variations, parasitics, and thermal noise. The work demonstrates substantial speedups and hardware-efficiency advantages over prior analog solvers, while highlighting design tradeoffs between accuracy, speed, and hardware complexity, and showing strong potential for in-memory linear algebra in SPD regimes. These results point to a scalable, matrix-property-driven pathway to hardware-accelerated linear solvers that leverage resistive networks and cross-point CIM for rapid, energy-efficient computations.

Abstract

Accelerating the solution of linear systems of equations is critical due to their central role in numerous applications, such as numerical simulations, data analytics, and machine learning. This paper presents an analog solver circuit designed to accelerate the solution of symmetric positive definite (SPD) linear systems of equations. The proposed design leverages noninverting operational amplifier configurations to create a negative resistance circuit, effectively modeling any symmetric system. The paper details the principles behind the design, optimizations of the system architecture, and numerical results that demonstrate the robustness of the design. The findings reveal that the proposed system solves symmetric diagonally dominant (SDD) matrices with O(1) complexity, achieving the theoretical maximum speed as the circuit relies solely on resistors. For non-diagonally dominant SPD systems, the solution speed depends on matrix properties, specifically eigenvalues and diagonal dominance deviation, but remains independent of the size of the matrix.

Analog Solver Circuit for Linear Symmetric Positive-Definite Systems at a Complexity Independent of Matrix Size

TL;DR

The paper introduces a novel analog compute-in-memory solver that directly maps SPD linear systems to a resistive network, achieving unprecedented speed by transforming to a formulation that minimizes active (negative) components. For symmetric diagonally dominant (SDD) matrices the network becomes purely passive, yielding -time convergence, while for general SPD matrices the convergence is independent of problem size and governed by spectral properties such as the smallest eigenvalue and diagonal dominance deviation. The design uses a cross-point memristor array and a carefully chosen diagonal matrix to ensure positive definiteness and efficient hardware mapping, with extensive SPICE and Monte Carlo-style robustness analyses under device variations, parasitics, and thermal noise. The work demonstrates substantial speedups and hardware-efficiency advantages over prior analog solvers, while highlighting design tradeoffs between accuracy, speed, and hardware complexity, and showing strong potential for in-memory linear algebra in SPD regimes. These results point to a scalable, matrix-property-driven pathway to hardware-accelerated linear solvers that leverage resistive networks and cross-point CIM for rapid, energy-efficient computations.

Abstract

Accelerating the solution of linear systems of equations is critical due to their central role in numerous applications, such as numerical simulations, data analytics, and machine learning. This paper presents an analog solver circuit designed to accelerate the solution of symmetric positive definite (SPD) linear systems of equations. The proposed design leverages noninverting operational amplifier configurations to create a negative resistance circuit, effectively modeling any symmetric system. The paper details the principles behind the design, optimizations of the system architecture, and numerical results that demonstrate the robustness of the design. The findings reveal that the proposed system solves symmetric diagonally dominant (SDD) matrices with O(1) complexity, achieving the theoretical maximum speed as the circuit relies solely on resistors. For non-diagonally dominant SPD systems, the solution speed depends on matrix properties, specifically eigenvalues and diagonal dominance deviation, but remains independent of the size of the matrix.

Paper Structure

This paper contains 31 sections, 83 equations, 20 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Existing Paradigms for Solving Large Systems of Equations
  3. Novel Approach Using Configurable Network of Resistors
  4. Background
  5. Equivalent Resistive Network
  6. Negative Resistance Circuit
  7. Preliminary Design: $n$-unknowns
  8. Right-Hand-Side: $(b-K_s x)$
  9. Left-Hand-Side: $(A-K_s)x$
  10. System Testing
  11. Proposed Design: $2n$-unknowns
  12. Choice of $D$-Matrix
  13. Positive Definiteness Condition
  14. Scaling
  15. Proposed $D$-Matrix
  16. ...and 16 more sections

Figures (20)

  • Figure 1: A resistive network example for a 3x3 system $Ax=b$. The unknown vector $x$ represents the voltage at the nodes, while the right hand side vector $b$ represents the external current going in to the nodes. The matrix $A$ represents the conductance of the resistors between the nodes.
  • Figure 2: Theoretical construction of a resistive network for a given 3x3 system $Ax=b$. The unknown vector $x$ represents the voltage at the nodes, while the right hand side vector $b$ represents the external current going into the nodes. Conductance of the resistors are obtained from the components of $A$.
  • Figure 3: Negative Resistance Circuit with buffers $i_{ie}=i_{je}=0$
  • Figure 4: Resistive network for a 3x3 system $(A-K_s)x=b-K_sx$. The current sources are replaced with voltage sources and resistors.
  • Figure 5: Right-Hand-Side Circuit for each node. Each node $i$ is connected to a supply resistor of conductance $k_{si}$ that is connected to either $x_s^+$ in case $b_i$ is positive or $x_s^-$ in case $b_i$ is negative. In the case of $b_i=0$, the switch is not enabled.
  • ...and 15 more figures