OpenYield: An Open-Source SRAM Yield Analysis and Optimization Benchmark Suite

TL;DR

OpenYield addresses the reproducibility and transferability gap in SRAM yield analysis by delivering an open-source, high-fidelity benchmark suite. It combines a hierarchical SRAM circuit generator that includes second-order effects, a standardized yield-analysis platform with MC and importance-sampling baselines, and a transistor-sizing optimization suite with multiple optimization algorithms. The framework demonstrates that parasitics, inter-cell leakage, and peripheral variations markedly alter read/write margins, delay, and power, and shows that optimization under these realistic models yields substantial gains while revealing the limitations of simplified models. By providing open benchmarks and reference implementations, OpenYield enables reproducible, fair comparisons and accelerates robust SRAM design methodologies for future technology nodes.

Abstract

Static Random-Access Memory (SRAM) yield analysis is essential for semiconductor innovation, yet research progress faces a critical challenge: the large gap between simplified academic models and the complexities observed in practice. The lack of open, higher-fidelity benchmarks has hindered reproducibility and transferability, as promising academic techniques often fail to carry over to more realistic settings. We present OpenYield, an open-source ecosystem that aims to narrow this gap through three contributions: (i) An SRAM circuit generator that explicitly incorporates second-order effects (interconnect/line parasitics, inter-cell leakage coupling, and peripheral-circuit variations) that are commonly omitted in academic studies. (ii) A standardized evaluation platform with a simple interface and baseline yield-analysis implementations to enable fair comparisons and reproducible research on these higher-fidelity circuits. (iii) An optimization platform for transistor-level sizing under these models, supporting reproducible studies of robustness/efficiency trade-offs. OpenYield aims to foster more reproducible and transferable progress in SRAM-yield research. The framework is publicly available at https://github.com/ShenShan123/OpenYield

Figures (11)

• Figure 1: Overview of OpenYield's ecosystem showing the circuit generator, baseline yield analysis algorithms, and transistor-sizing optimization framework.
• Figure 2: Schematics of a 6T SRAM cell under read and write operations.
• Figure 3: Butterfly curves using DC analysis. The waveforms have been rotated by 45$^\circ$ as SNM is defined by the largest vertical distance between V1 and V2.
• Figure 4: Read and write operation under process variation.
• Figure 5: Mean read/write access delay and average read/write power consumption for a 4-column SRAM array as a function of the number of rows (8 to 256).