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Optimization and Synthesis of Quantum Circuits with Global Gates

Alejandro Villoria, Henning Basold, Alfons Laarman

TL;DR

This work tackles hardware-aware quantum circuit compilation for ion-trap devices by harnessing the ZX-calculus to extract circuits that minimize the number of global $GMS$ gates. The proposed pipeline converts arbitrary circuits into graph-like ZX diagrams, preserves gflow, and uses a linear program plus peephole optimizations to group entangling gates into as few $GMS$ gates as possible, while outputting a circuit in the hardware's native gate set. The authors implement the approach in PyZX, benchmark it against naive compilation and Qiskit, and demonstrate substantial reductions in entangling-gate counts across multiple circuit families, albeit with some circuits where structure hinders global-gate grouping. The results suggest that ZX-based synthesis can meaningfully improve execution time and fidelity on ion-trap platforms by leveraging all-to-all connectivity and the ability to execute $GMS$ gates, with practical impact for NISQ-era quantum computing.

Abstract

Compiling quantum circuits to account for hardware restrictions is an essential part of the quantum computing stack. Circuit compilation allows us to adapt algorithm descriptions into a sequence of operations supported by real quantum hardware, and has the potential to significantly improve their performance when optimization techniques are added to the process. One such optimization technique is reducing the number of quantum gates that are needed to execute a circuit. For instance, methods for reducing the number of non-Clifford gates or CNOT gates from a circuit is an extensive research area that has gathered significant interest over the years. For certain hardware platforms such as ion trap quantum computers, we can leverage some of their special properties to further reduce the cost of executing a quantum circuit in them. In this work we use global interactions, such as the Global Mølmer-Sørensen gate present in ion trap hardware, to optimize and synthesize quantum circuits. We design and implement an algorithm that is able to compile an arbitrary quantum circuit into another circuit that uses global gates as the entangling operation, while optimizing the number of global interactions needed. The algorithm is based on the ZX-calculus and uses an specialized circuit extraction routine that groups entangling gates into Global Mølmer-Sørensen gates. We benchmark the algorithm in a variety of circuits, and show how it improves their performance under state-of-the-art hardware considerations in comparison to a naive algorithm and the Qiskit optimizer.

Optimization and Synthesis of Quantum Circuits with Global Gates

TL;DR

This work tackles hardware-aware quantum circuit compilation for ion-trap devices by harnessing the ZX-calculus to extract circuits that minimize the number of global gates. The proposed pipeline converts arbitrary circuits into graph-like ZX diagrams, preserves gflow, and uses a linear program plus peephole optimizations to group entangling gates into as few gates as possible, while outputting a circuit in the hardware's native gate set. The authors implement the approach in PyZX, benchmark it against naive compilation and Qiskit, and demonstrate substantial reductions in entangling-gate counts across multiple circuit families, albeit with some circuits where structure hinders global-gate grouping. The results suggest that ZX-based synthesis can meaningfully improve execution time and fidelity on ion-trap platforms by leveraging all-to-all connectivity and the ability to execute gates, with practical impact for NISQ-era quantum computing.

Abstract

Compiling quantum circuits to account for hardware restrictions is an essential part of the quantum computing stack. Circuit compilation allows us to adapt algorithm descriptions into a sequence of operations supported by real quantum hardware, and has the potential to significantly improve their performance when optimization techniques are added to the process. One such optimization technique is reducing the number of quantum gates that are needed to execute a circuit. For instance, methods for reducing the number of non-Clifford gates or CNOT gates from a circuit is an extensive research area that has gathered significant interest over the years. For certain hardware platforms such as ion trap quantum computers, we can leverage some of their special properties to further reduce the cost of executing a quantum circuit in them. In this work we use global interactions, such as the Global Mølmer-Sørensen gate present in ion trap hardware, to optimize and synthesize quantum circuits. We design and implement an algorithm that is able to compile an arbitrary quantum circuit into another circuit that uses global gates as the entangling operation, while optimizing the number of global interactions needed. The algorithm is based on the ZX-calculus and uses an specialized circuit extraction routine that groups entangling gates into Global Mølmer-Sørensen gates. We benchmark the algorithm in a variety of circuits, and show how it improves their performance under state-of-the-art hardware considerations in comparison to a naive algorithm and the Qiskit optimizer.

Paper Structure

This paper contains 23 sections, 4 theorems, 9 equations, 4 figures, 1 table, 1 algorithm.

Key Result

Proposition 1

Let $\operatorname{CNOT}_{i_n,j_n}\dots\operatorname{CNOT}_{i_1,j_1}$ be a linear reversible circuit consisting of commuting CNOT gates. This circuit can always be compiled with one global gate plus single-qubit gates.

Figures (4)

  • Figure 1: Four of the rules of the ZX-calculus. A complete ruleset can be found in vilmart-near-optimal-2018.
  • Figure 2: From quantum circuit to graph-like ZX-diagram. We turned the ZX-diagram into graph-like form by applying the rules of \ref{['fig:ruleset']} and interpreting Hadamard gates as Hadamard edges.
  • Figure 3: An example of circuit extraction. In the first equation we simplify the connectivity of $v$ using two CNOT gates. In the second equation we extract the Hadamard gate corresponding to the Hadamard edge $(v,w)$, an $R_Z$ due to the phase of $w$, and a $CZ$ due to the Hadamard edge between $w$ and the second frontier vertex. These steps would be repeated until there is no more diagram to be extracted.
  • Figure 4: Examples of the circuit equivalences given in this section at a glance. In the first row we show how to implement a CZ and a CNOT using two-qubit rotations. In the subsequent rows we show an example of implementing a layer of CZ gates, a fanout gate, and a layer of commuting CNOTs using a single GZZ or GMS gate.

Theorems & Definitions (11)

  • Proposition 1
  • proof
  • Proposition 2
  • proof
  • Proposition 3
  • proof
  • Proposition 4
  • proof
  • Definition 1: duncan-graph-theoretic-2020, Definition 3.1.
  • Definition 2: Adapted from backens-there-2021
  • ...and 1 more