ChipletPart: Cost-Aware Partitioning for 2.5D Systems

TL;DR

This work introduces ChipletPart — a cost-driven 2.5D system partitioner that addresses the unique constraints of chiplet systems, including complex objective functions, limited reach of inter-chiplet I/O transceivers, and the assignment of heterogeneous manufacturing technologies to different chiplets.

Abstract

Industry adoption of chiplets has been growing as chiplets are a cost-effective option for making large, high-performance systems. Consequently, partitioning large systems into chiplets is increasingly important. In this work, we introduce ChipletPart, a cost-driven 2.5D system partitioner that addresses the constraints of chiplet systems, including complex objective functions, limited reach of inter-chiplet I/O transceivers, and the assignment of heterogeneous manufacturing technologies to different chiplets. ChipletPart integrates a sophisticated chiplet cost model with a genetic algorithm (GA)-based technology assignment and partitioning methodology, along with a simulated annealing (SA)-based chiplet floorplanner. Our results show that ChipletPart: (i) reduces chiplet cost by up to 58% (20% geometric mean) compared to state-of-the-art min-cut partitioners, which often yield floorplan-infeasible solutions; (ii) generates partitions with up to 47% (6% geometric mean) lower cost compared to the prior work Floorplet; (iii) reduces chiplet cost up to 48% (30% geometric mean) compared to Chipletizer, while consistently producing I/O-feasible chiplet solutions across all testcases; and (iv) for the testcases we study, heterogeneous integration reduces cost by up to 43% (15% geometric mean) compared to homogeneous implementations. Additionally, we explore Bayesian optimization (BO) for finding low cost and floorplan-feasible chiplet solutions with technology assignments. On some testcases, our BO framework achieves better system cost (up to 5.3% improvement) with higher runtime overhead (up to 4x) compared to our GA-based framework. We also present case studies that show how changes in packaging and inter-chiplet signaling technologies can affect partitioning solutions. Finally, ChipletPart, the underlying cost model, and our testcase generator are available as open-source tools.

Figures (14)

• Figure 1: Generic example of block-level chiplet partitioning. Left: an IP block-level netlist (different types of IP blocks shown in different colors). Right: an integrated 2.5D chiplet system reflecting the block-level netlist partitioning with technology node assignment shown in different colors.
• Figure 2: ChipletPart Framework. Core-ChipletPart is shown in Figure \ref{['fig:core_chipletpart']}. Partitioning refinement is shown in Figure \ref{['fig:cost_fm']}.
• Figure 3: GA-based technology assignment. A genome is a set of technology nodes. Shown: two parent genomes $\langle 7, 7, 14 \rangle$ and $\langle 10, \textcolor{black}{10}, 10 \rangle$ undergo crossover to produce the offspring $\langle 7, 10, 14 \rangle$; the offspring undergoes mutation to produce $\langle 10, 10, 7 \rangle$ for the next-generation population.
• Figure 4: Illustration of reach. Wirelengths: black - 1 $\text{mm}$, orange - 7 $\text{mm}$, blue - 13 $\text{mm}$, and green - 19 $\text{mm}$.
• Figure 5: Core-ChipletPart partitioning flow. We use multiple techniques to generate the initial partitions, then we prune out the worst-performing initializations before running refinement.