An RFSoC-based F-engine for ARGOS

TL;DR

This work addresses the challenge of real-time, cost-effective backends for large arrays of small dishes by delivering the first-stage F-engine for the ARGOS demonstrator on an RFSoC4x2. The authors implement digitization, $8$-tap polyphase filter bank channelization with a $2048$-point FFT, plus coarse and fine delay corrections and frequency-dependent complex gain calibration, producing delay- and phase-corrected dual-polarization channelized voltages across $1$-$3$ GHz with $1$ MHz channels at $2\, \mathrm{GSPS}$. Hardware verification confirms the PFB channel response matches theory, and delay correction is validated with synthetic tests; a commensal pulsar observation at Effelsberg demonstrates practical performance in an operational setting. The study also demonstrates the viability of high-level synthesis for rapid FPGA backend development in radio astronomy. Overall, this work provides a scalable, low-power, and adaptable path toward real-time processing for next-generation small-D, big-N interferometers like ARGOS, with potential applicability to other large arrays.

Abstract

Radio interferometers provide the means to perform the wide-field-of-view (FoV), high-sensitivity observations required for modern radio surveys. As computing power per cost has decreased, there has been a move towards larger arrays of smaller dishes, such as DSA-2000, the upcoming HIRAX, CHORD and SKA radio telescopes. Such arrays can have simpler receiver designs with room-temperature low-noise amplifiers and direct sampling to achieve, greatly reducing the cost per antenna. The ARGOS project is currently developing an array of five 6-meter antennas that will be used to demonstrate the technology required for a next generation "small-D, big-N" radio interferometer in Europe. In this work, our objective was to implement a first-stage digital signal processing system for the ARGOS demonstrator array, providing digitization, channelization, delay correction and frequency-dependent complex gain correction. The system is intended to produce delay and phase corrected dual-polarization channelized voltages in the frequency range 1-3 GHz with a nominal channel bandwidth of 1 MHz. We use an RFSoC 4x2 evaluation board with four analog-to-digital converters (ADCs) that can simultaneously sample two 1 GHz, dual-polarization bands. We use Xilinx Vitis HLS C++ to develop the required firmware as a set of customizable modules suitable for rapid prototyping. We performed hardware verification of the channel response of the critically sampled PFB and of the delay correction, showing both to be consistent with theoretical expectations. Furthermore, the board was installed at the Effelsberg 100-meter radio telescope where we performed commensal pulsar observations with the Effelsberg Direct Digitization backend, showing comparable performance. This work demonstrates the utility of high-level synthesis (HLS) languages in the development of high performance radio astronomy processing backends.

Figures (9)

• Figure 1: Dataflow diagram of the F-engine design. The dual-band and dual-polarization voltages are digitized by ADCs and then processed sequentially by the 8-tap FIR filter, coarse delay corrector, FFT block, and fine delay corrector. The four data streams are then merged and transposed in the corner turner before being packetized and transferred through the 100G network interface.
• Figure 2: Diagram illustrating the algorithm of a critically sampled polyphase filterbank (PFB). The input stream is segmented into frames of $M$ samples. At each step, a window of $P$ consecutive frames is multiplied by predefined filter coefficients, advanced by one frame per iteration. The filtered outputs are summed across the $P$ frames to yield a single $M$-sample frame, which is then transformed via FFT.
• Figure 3: Diagram illustrating the algorithm of the coarse delay correction. The input data stream is continually written in a ring buffer, while the buffer is read into the output data stream with a shift starting position based on integer delay setup, which can be updated on the fly.
• Figure 4: Diagram illustrating the algorithm of the corner turner. The corner turner performs transposition between time and frequency dimension in blocks of 512 spectra in two stages, with each stage transposing the data of fractional spectra.
• Figure 5: Measured channel frequency response of the critically sampled PFB. The upper panel shows the phase response and the bottom panel shows the amplitude response. The thin blue solid line represents the measured channel response, while the thick purple solid line represents the theoretical channel response. The yellow dashed lines represent the edges of one channel.