Scalable native multiqubit gates via engineered noncomputational-state interactions in superconducting fluxonium qubits
Peng Zhao, Peng Xu, Zheng-Yuan Xue
TL;DR
This work tackles the challenge of implementing native multi-qubit gates in superconducting qubits by leveraging engineered interactions in noncomputational manifolds of fluxonium qubits to realize $C^{\otimes N}Z$ gates. The authors derive an effective Hamiltonian in a central-fluxonium–neighbor architecture and show that neighbor-state-dependent plasmon frequency shifts enable selective activation of multi-qubit transitions. They demonstrate, through analysis and simulations, that CCZ, CCCZ, and CCCCZ gates with high fidelity can be executed rapidly (tens to a few hundred nanoseconds) while coexisting with primitive gates, with gate errors on the order of $10^{-2}$ (or $10^{-3}$ when incoherence is considered) for $N=1$–$4$. The results indicate a scalable route to integrate native multi-qubit gates into a unified processor, potentially reducing circuit depth and overhead for near-term and fault-tolerant quantum computing, though larger $N$ faces engineering challenges from level repulsion and capacitive loading.
Abstract
Native multiqubit gates could be essential for bridging the gap from current noisy devices to future utility-scale quantum computers, as they can substantially reduce circuit depth for near-term applications on noisy devices and may also lower the physical overhead of fault-tolerant quantum computation. Here we introduce a scalable protocol for implementing native multi-controlled gates on fluxonium qubits, supporting an arbitrary number of control qubits ($N > 1$) while remaining compatible with existing single- and two-qubit gate realizations. Our approach leverages engineered interactions in noncomputational state manifolds to enable qubit-state selective transitions, which is activated for the direct implementation of $(C^{\otimes N})Z$ gates. We show that in square lattices with fluxonium qubits, $CCZ$, $CCCZ$, and $CCCCZ$ gates with errors around 0.01 (0.001) are achievable, with gate lengths of $50\,(100)\,\text{ns}$, $100\,(250)\,\text{ns}$, and $150\,(300)\,\text{ns}$, respectively. Looking forward, integrating these native multi-controlled gates with primitive single- and two-qubit gate sets within a single quantum processor could significantly enhance flexibility in circuit synthesis and offer a promising alternative pathway toward utility-scale quantum computing.
